linux/drivers/staging/most/dim2/hal.c

// SPDX-License-Identifier: GPL-2.0
/*
 * hal.c - DIM2 HAL implementation
 * (MediaLB, Device Interface Macro IP, OS62420)
 *
 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
 */

/* Author: Andrey Shvetsov <[email protected]> */

#include "hal.h"
#include "errors.h"
#include "reg.h"
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/io.h>

/*
 * Size factor for isochronous DBR buffer.
 * Minimal value is 3.
 */
#define ISOC_DBR_FACTOR

/*
 * Number of 32-bit units for DBR map.
 *
 * 1: block size is 512, max allocation is 16K
 * 2: block size is 256, max allocation is 8K
 * 4: block size is 128, max allocation is 4K
 * 8: block size is 64, max allocation is 2K
 *
 * Min allocated space is block size.
 * Max possible allocated space is 32 blocks.
 */
#define DBR_MAP_SIZE

/* -------------------------------------------------------------------------- */
/* not configurable area */

#define CDT
#define ADT
#define MLB_CAT
#define AHB_CAT

#define DBR_SIZE
#define DBR_BLOCK_SIZE

#define ROUND_UP_TO(x, d)

/* -------------------------------------------------------------------------- */
/* generic helper functions and macros */

static inline u32 bit_mask(u8 position)
{}

static inline bool dim_on_error(u8 error_id, const char *error_message)
{}

/* -------------------------------------------------------------------------- */
/* types and local variables */

struct async_tx_dbr {};

struct lld_global_vars_t {};

static struct lld_global_vars_t g =;

/* -------------------------------------------------------------------------- */

static int dbr_get_mask_size(u16 size)
{}

/**
 * alloc_dbr() - Allocates DBR memory.
 * @size: Allocating memory size.
 * Returns: Offset in DBR memory by success or DBR_SIZE if out of memory.
 */
static int alloc_dbr(u16 size)
{}

static void free_dbr(int offs, int size)
{}

/* -------------------------------------------------------------------------- */

static void dim2_transfer_madr(u32 val)
{}

static void dim2_clear_dbr(u16 addr, u16 size)
{}

static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx)
{}

static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)
{}

static inline void dim2_write_ctr(u32 ctr_addr, const u32 *value)
{}

static inline void dim2_clear_ctr(u32 ctr_addr)
{}

static void dim2_configure_cat(u8 cat_base, u8 ch_addr, u8 ch_type,
			       bool read_not_write)
{}

static void dim2_clear_cat(u8 cat_base, u8 ch_addr)
{}

static void dim2_configure_cdt(u8 ch_addr, u16 dbr_address, u16 hw_buffer_size,
			       u16 packet_length)
{}

static u16 dim2_rpc(u8 ch_addr)
{}

static void dim2_clear_cdt(u8 ch_addr)
{}

static void dim2_configure_adt(u8 ch_addr)
{}

static void dim2_clear_adt(u8 ch_addr)
{}

static void dim2_start_ctrl_async(u8 ch_addr, u8 idx, u32 buf_addr,
				  u16 buffer_size)
{}

static void dim2_start_isoc_sync(u8 ch_addr, u8 idx, u32 buf_addr,
				 u16 buffer_size)
{}

static void dim2_clear_ctram(void)
{}

static void dim2_configure_channel(u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address,
				   u16 hw_buffer_size, u16 packet_length)
{}

static void dim2_clear_channel(u8 ch_addr)
{}

/* -------------------------------------------------------------------------- */
/* trace async tx dbr fill state */

static inline u16 norm_pc(u16 pc)
{}

static void dbrcnt_init(u8 ch_addr, u16 dbr_size)
{}

static void dbrcnt_enq(int buf_sz)
{}

u16 dim_dbr_space(struct dim_channel *ch)
{}

/* -------------------------------------------------------------------------- */
/* channel state helpers */

static void state_init(struct int_ch_state *state)
{}

/* -------------------------------------------------------------------------- */
/* macro helper functions */

static inline bool check_channel_address(u32 ch_address)
{}

static inline bool check_packet_length(u32 packet_length)
{}

static inline bool check_bytes_per_frame(u32 bytes_per_frame)
{}

u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
{}

static inline u16 norm_isoc_buffer_size(u16 buf_size, u16 packet_length)
{}

static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame)
{}

static void dim2_cleanup(void)
{}

static void dim2_initialize(bool enable_6pin, u8 mlb_clock)
{}

static bool dim2_is_mlb_locked(void)
{}

/* -------------------------------------------------------------------------- */
/* channel help routines */

static inline bool service_channel(u8 ch_addr, u8 idx)
{}

/* -------------------------------------------------------------------------- */
/* channel init routines */

static void isoc_init(struct dim_channel *ch, u8 ch_addr, u16 packet_length)
{}

static void sync_init(struct dim_channel *ch, u8 ch_addr, u16 bytes_per_frame)
{}

static void channel_init(struct dim_channel *ch, u8 ch_addr)
{}

/* returns true if channel interrupt state is cleared */
static bool channel_service_interrupt(struct dim_channel *ch)
{}

static bool channel_start(struct dim_channel *ch, u32 buf_addr, u16 buf_size)
{}

static u8 channel_service(struct dim_channel *ch)
{}

static bool channel_detach_buffers(struct dim_channel *ch, u16 buffers_number)
{}

/* -------------------------------------------------------------------------- */
/* API */

u8 dim_startup(struct dim2_regs __iomem *dim_base_address, u32 mlb_clock,
	       u32 fcnt)
{}

void dim_shutdown(void)
{}

bool dim_get_lock_state(void)
{}

static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx,
			  u16 ch_address, u16 hw_buffer_size)
{}

void dim_service_mlb_int_irq(void)
{}

/*
 * Retrieves maximal possible correct buffer size for isochronous data type
 * conform to given packet length and not bigger than given buffer size.
 *
 * Returns non-zero correct buffer size or zero by error.
 */
u16 dim_norm_isoc_buffer_size(u16 buf_size, u16 packet_length)
{}

/*
 * Retrieves maximal possible correct buffer size for synchronous data type
 * conform to given bytes per frame and not bigger than given buffer size.
 *
 * Returns non-zero correct buffer size or zero by error.
 */
u16 dim_norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame)
{}

u8 dim_init_control(struct dim_channel *ch, u8 is_tx, u16 ch_address,
		    u16 max_buffer_size)
{}

u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address,
		  u16 max_buffer_size)
{}

u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address,
		 u16 packet_length)
{}

u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address,
		 u16 bytes_per_frame)
{}

u8 dim_destroy_channel(struct dim_channel *ch)
{}

void dim_service_ahb_int_irq(struct dim_channel *const *channels)
{}

u8 dim_service_channel(struct dim_channel *ch)
{}

struct dim_ch_state *dim_get_channel_state(struct dim_channel *ch,
					   struct dim_ch_state *state_ptr)
{}

bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr,
			u16 buffer_size)
{}

bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number)
{}