/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright (c) 2021 MediaTek Inc. * Author: Chun-Jie Chen <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8195_H #define _DT_BINDINGS_CLK_MT8195_H /* TOPCKGEN */ #define CLK_TOP_AXI … #define CLK_TOP_SPM … #define CLK_TOP_SCP … #define CLK_TOP_BUS_AXIMEM … #define CLK_TOP_VPP … #define CLK_TOP_ETHDR … #define CLK_TOP_IPE … #define CLK_TOP_CAM … #define CLK_TOP_CCU … #define CLK_TOP_IMG … #define CLK_TOP_CAMTM … #define CLK_TOP_DSP … #define CLK_TOP_DSP1 … #define CLK_TOP_DSP2 … #define CLK_TOP_DSP3 … #define CLK_TOP_DSP4 … #define CLK_TOP_DSP5 … #define CLK_TOP_DSP6 … #define CLK_TOP_DSP7 … #define CLK_TOP_IPU_IF … #define CLK_TOP_MFG_CORE_TMP … #define CLK_TOP_CAMTG … #define CLK_TOP_CAMTG2 … #define CLK_TOP_CAMTG3 … #define CLK_TOP_CAMTG4 … #define CLK_TOP_CAMTG5 … #define CLK_TOP_UART … #define CLK_TOP_SPI … #define CLK_TOP_SPIS … #define CLK_TOP_MSDC50_0_HCLK … #define CLK_TOP_MSDC50_0 … #define CLK_TOP_MSDC30_1 … #define CLK_TOP_MSDC30_2 … #define CLK_TOP_INTDIR … #define CLK_TOP_AUD_INTBUS … #define CLK_TOP_AUDIO_H … #define CLK_TOP_PWRAP_ULPOSC … #define CLK_TOP_ATB … #define CLK_TOP_PWRMCU … #define CLK_TOP_DP … #define CLK_TOP_EDP … #define CLK_TOP_DPI … #define CLK_TOP_DISP_PWM0 … #define CLK_TOP_DISP_PWM1 … #define CLK_TOP_USB_TOP … #define CLK_TOP_SSUSB_XHCI … #define CLK_TOP_USB_TOP_1P … #define CLK_TOP_SSUSB_XHCI_1P … #define CLK_TOP_USB_TOP_2P … #define CLK_TOP_SSUSB_XHCI_2P … #define CLK_TOP_USB_TOP_3P … #define CLK_TOP_SSUSB_XHCI_3P … #define CLK_TOP_I2C … #define CLK_TOP_SENINF … #define CLK_TOP_SENINF1 … #define CLK_TOP_SENINF2 … #define CLK_TOP_SENINF3 … #define CLK_TOP_GCPU … #define CLK_TOP_DXCC … #define CLK_TOP_DPMAIF_MAIN … #define CLK_TOP_AES_UFSFDE … #define CLK_TOP_UFS … #define CLK_TOP_UFS_TICK1US … #define CLK_TOP_UFS_MP_SAP_CFG … #define CLK_TOP_VENC … #define CLK_TOP_VDEC … #define CLK_TOP_PWM … #define CLK_TOP_MCUPM … #define CLK_TOP_SPMI_P_MST … #define CLK_TOP_SPMI_M_MST … #define CLK_TOP_DVFSRC … #define CLK_TOP_TL … #define CLK_TOP_TL_P1 … #define CLK_TOP_AES_MSDCFDE … #define CLK_TOP_DSI_OCC … #define CLK_TOP_WPE_VPP … #define CLK_TOP_HDCP … #define CLK_TOP_HDCP_24M … #define CLK_TOP_HD20_DACR_REF_CLK … #define CLK_TOP_HD20_HDCP_CCLK … #define CLK_TOP_HDMI_XTAL … #define CLK_TOP_HDMI_APB … #define CLK_TOP_SNPS_ETH_250M … #define CLK_TOP_SNPS_ETH_62P4M_PTP … #define CLK_TOP_SNPS_ETH_50M_RMII … #define CLK_TOP_DGI_OUT … #define CLK_TOP_NNA0 … #define CLK_TOP_NNA1 … #define CLK_TOP_ADSP … #define CLK_TOP_ASM_H … #define CLK_TOP_ASM_M … #define CLK_TOP_ASM_L … #define CLK_TOP_APLL1 … #define CLK_TOP_APLL2 … #define CLK_TOP_APLL3 … #define CLK_TOP_APLL4 … #define CLK_TOP_APLL5 … #define CLK_TOP_I2SO1_MCK … #define CLK_TOP_I2SO2_MCK … #define CLK_TOP_I2SI1_MCK … #define CLK_TOP_I2SI2_MCK … #define CLK_TOP_DPTX_MCK … #define CLK_TOP_AUD_IEC_CLK … #define CLK_TOP_A1SYS_HP … #define CLK_TOP_A2SYS_HF … #define CLK_TOP_A3SYS_HF … #define CLK_TOP_A4SYS_HF … #define CLK_TOP_SPINFI_BCLK … #define CLK_TOP_NFI1X … #define CLK_TOP_ECC … #define CLK_TOP_AUDIO_LOCAL_BUS … #define CLK_TOP_SPINOR … #define CLK_TOP_DVIO_DGI_REF … #define CLK_TOP_ULPOSC … #define CLK_TOP_ULPOSC_CORE … #define CLK_TOP_SRCK … #define CLK_TOP_MFG_CK_FAST_REF … #define CLK_TOP_CLK26M_D2 … #define CLK_TOP_CLK26M_D52 … #define CLK_TOP_IN_DGI … #define CLK_TOP_IN_DGI_D2 … #define CLK_TOP_IN_DGI_D4 … #define CLK_TOP_IN_DGI_D6 … #define CLK_TOP_IN_DGI_D8 … #define CLK_TOP_MAINPLL_D3 … #define CLK_TOP_MAINPLL_D4 … #define CLK_TOP_MAINPLL_D4_D2 … #define CLK_TOP_MAINPLL_D4_D4 … #define CLK_TOP_MAINPLL_D4_D8 … #define CLK_TOP_MAINPLL_D5 … #define CLK_TOP_MAINPLL_D5_D2 … #define CLK_TOP_MAINPLL_D5_D4 … #define CLK_TOP_MAINPLL_D5_D8 … #define CLK_TOP_MAINPLL_D6 … #define CLK_TOP_MAINPLL_D6_D2 … #define CLK_TOP_MAINPLL_D6_D4 … #define CLK_TOP_MAINPLL_D6_D8 … #define CLK_TOP_MAINPLL_D7 … #define CLK_TOP_MAINPLL_D7_D2 … #define CLK_TOP_MAINPLL_D7_D4 … #define CLK_TOP_MAINPLL_D7_D8 … #define CLK_TOP_MAINPLL_D9 … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D4 … #define CLK_TOP_UNIVPLL_D4_D2 … #define CLK_TOP_UNIVPLL_D4_D4 … #define CLK_TOP_UNIVPLL_D4_D8 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D5_D2 … #define CLK_TOP_UNIVPLL_D5_D4 … #define CLK_TOP_UNIVPLL_D5_D8 … #define CLK_TOP_UNIVPLL_D6 … #define CLK_TOP_UNIVPLL_D6_D2 … #define CLK_TOP_UNIVPLL_D6_D4 … #define CLK_TOP_UNIVPLL_D6_D8 … #define CLK_TOP_UNIVPLL_D6_D16 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_192M … #define CLK_TOP_UNIVPLL_192M_D4 … #define CLK_TOP_UNIVPLL_192M_D8 … #define CLK_TOP_UNIVPLL_192M_D16 … #define CLK_TOP_UNIVPLL_192M_D32 … #define CLK_TOP_APLL1_D3 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL2_D3 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL3_D4 … #define CLK_TOP_APLL4_D4 … #define CLK_TOP_APLL5_D4 … #define CLK_TOP_HDMIRX_APLL_D3 … #define CLK_TOP_HDMIRX_APLL_D4 … #define CLK_TOP_HDMIRX_APLL_D6 … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D4_D2 … #define CLK_TOP_MMPLL_D4_D4 … #define CLK_TOP_MMPLL_D5 … #define CLK_TOP_MMPLL_D5_D2 … #define CLK_TOP_MMPLL_D5_D4 … #define CLK_TOP_MMPLL_D6 … #define CLK_TOP_MMPLL_D6_D2 … #define CLK_TOP_MMPLL_D7 … #define CLK_TOP_MMPLL_D9 … #define CLK_TOP_TVDPLL1_D2 … #define CLK_TOP_TVDPLL1_D4 … #define CLK_TOP_TVDPLL1_D8 … #define CLK_TOP_TVDPLL1_D16 … #define CLK_TOP_TVDPLL2_D2 … #define CLK_TOP_TVDPLL2_D4 … #define CLK_TOP_TVDPLL2_D8 … #define CLK_TOP_TVDPLL2_D16 … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D4 … #define CLK_TOP_MSDCPLL_D16 … #define CLK_TOP_ETHPLL_D2 … #define CLK_TOP_ETHPLL_D8 … #define CLK_TOP_ETHPLL_D10 … #define CLK_TOP_DGIPLL_D2 … #define CLK_TOP_ULPOSC1 … #define CLK_TOP_ULPOSC1_D2 … #define CLK_TOP_ULPOSC1_D4 … #define CLK_TOP_ULPOSC1_D7 … #define CLK_TOP_ULPOSC1_D8 … #define CLK_TOP_ULPOSC1_D10 … #define CLK_TOP_ULPOSC1_D16 … #define CLK_TOP_ULPOSC2 … #define CLK_TOP_ADSPPLL_D2 … #define CLK_TOP_ADSPPLL_D4 … #define CLK_TOP_ADSPPLL_D8 … #define CLK_TOP_MEM_466M … #define CLK_TOP_MPHONE_SLAVE_B … #define CLK_TOP_PEXTP_PIPE … #define CLK_TOP_UFS_RX_SYMBOL … #define CLK_TOP_UFS_TX_SYMBOL … #define CLK_TOP_SSUSB_U3PHY_P1_P_P0 … #define CLK_TOP_UFS_RX_SYMBOL1 … #define CLK_TOP_FPC … #define CLK_TOP_HDMIRX_P … #define CLK_TOP_APLL12_DIV0 … #define CLK_TOP_APLL12_DIV1 … #define CLK_TOP_APLL12_DIV2 … #define CLK_TOP_APLL12_DIV3 … #define CLK_TOP_APLL12_DIV4 … #define CLK_TOP_APLL12_DIV9 … #define CLK_TOP_CFG_VPP0 … #define CLK_TOP_CFG_VPP1 … #define CLK_TOP_CFG_VDO0 … #define CLK_TOP_CFG_VDO1 … #define CLK_TOP_CFG_UNIPLL_SES … #define CLK_TOP_CFG_26M_VPP0 … #define CLK_TOP_CFG_26M_VPP1 … #define CLK_TOP_CFG_26M_AUD … #define CLK_TOP_CFG_AXI_EAST … #define CLK_TOP_CFG_AXI_EAST_NORTH … #define CLK_TOP_CFG_AXI_NORTH … #define CLK_TOP_CFG_AXI_SOUTH … #define CLK_TOP_CFG_EXT_TEST … #define CLK_TOP_SSUSB_REF … #define CLK_TOP_SSUSB_PHY_REF … #define CLK_TOP_SSUSB_P1_REF … #define CLK_TOP_SSUSB_PHY_P1_REF … #define CLK_TOP_SSUSB_P2_REF … #define CLK_TOP_SSUSB_PHY_P2_REF … #define CLK_TOP_SSUSB_P3_REF … #define CLK_TOP_SSUSB_PHY_P3_REF … #define CLK_TOP_NR_CLK … /* INFRACFG_AO */ #define CLK_INFRA_AO_PMIC_TMR … #define CLK_INFRA_AO_PMIC_AP … #define CLK_INFRA_AO_PMIC_MD … #define CLK_INFRA_AO_PMIC_CONN … #define CLK_INFRA_AO_SEJ … #define CLK_INFRA_AO_APXGPT … #define CLK_INFRA_AO_GCE … #define CLK_INFRA_AO_GCE2 … #define CLK_INFRA_AO_THERM … #define CLK_INFRA_AO_PWM_H … #define CLK_INFRA_AO_PWM1 … #define CLK_INFRA_AO_PWM2 … #define CLK_INFRA_AO_PWM3 … #define CLK_INFRA_AO_PWM4 … #define CLK_INFRA_AO_PWM … #define CLK_INFRA_AO_UART0 … #define CLK_INFRA_AO_UART1 … #define CLK_INFRA_AO_UART2 … #define CLK_INFRA_AO_UART3 … #define CLK_INFRA_AO_UART4 … #define CLK_INFRA_AO_GCE_26M … #define CLK_INFRA_AO_CQ_DMA_FPC … #define CLK_INFRA_AO_UART5 … #define CLK_INFRA_AO_HDMI_26M … #define CLK_INFRA_AO_SPI0 … #define CLK_INFRA_AO_MSDC0 … #define CLK_INFRA_AO_MSDC1 … #define CLK_INFRA_AO_CG1_MSDC2 … #define CLK_INFRA_AO_MSDC0_SRC … #define CLK_INFRA_AO_TRNG … #define CLK_INFRA_AO_AUXADC … #define CLK_INFRA_AO_CPUM … #define CLK_INFRA_AO_HDMI_32K … #define CLK_INFRA_AO_CEC_66M_H … #define CLK_INFRA_AO_IRRX … #define CLK_INFRA_AO_PCIE_TL_26M … #define CLK_INFRA_AO_MSDC1_SRC … #define CLK_INFRA_AO_CEC_66M_B … #define CLK_INFRA_AO_PCIE_TL_96M … #define CLK_INFRA_AO_DEVICE_APC … #define CLK_INFRA_AO_ECC_66M_H … #define CLK_INFRA_AO_DEBUGSYS … #define CLK_INFRA_AO_AUDIO … #define CLK_INFRA_AO_PCIE_TL_32K … #define CLK_INFRA_AO_DBG_TRACE … #define CLK_INFRA_AO_DRAMC_F26M … #define CLK_INFRA_AO_IRTX … #define CLK_INFRA_AO_SSUSB … #define CLK_INFRA_AO_DISP_PWM … #define CLK_INFRA_AO_CLDMA_B … #define CLK_INFRA_AO_AUDIO_26M_B … #define CLK_INFRA_AO_SPI1 … #define CLK_INFRA_AO_SPI2 … #define CLK_INFRA_AO_SPI3 … #define CLK_INFRA_AO_UNIPRO_SYS … #define CLK_INFRA_AO_UNIPRO_TICK … #define CLK_INFRA_AO_UFS_MP_SAP_B … #define CLK_INFRA_AO_PWRMCU … #define CLK_INFRA_AO_PWRMCU_BUS_H … #define CLK_INFRA_AO_APDMA_B … #define CLK_INFRA_AO_SPI4 … #define CLK_INFRA_AO_SPI5 … #define CLK_INFRA_AO_CQ_DMA … #define CLK_INFRA_AO_AES_UFSFDE … #define CLK_INFRA_AO_AES … #define CLK_INFRA_AO_UFS_TICK … #define CLK_INFRA_AO_SSUSB_XHCI … #define CLK_INFRA_AO_MSDC0_SELF … #define CLK_INFRA_AO_MSDC1_SELF … #define CLK_INFRA_AO_MSDC2_SELF … #define CLK_INFRA_AO_I2S_DMA … #define CLK_INFRA_AO_AP_MSDC0 … #define CLK_INFRA_AO_MD_MSDC0 … #define CLK_INFRA_AO_CG3_MSDC2 … #define CLK_INFRA_AO_GCPU … #define CLK_INFRA_AO_PCIE_PERI_26M … #define CLK_INFRA_AO_GCPU_66M_B … #define CLK_INFRA_AO_GCPU_133M_B … #define CLK_INFRA_AO_DISP_PWM1 … #define CLK_INFRA_AO_FBIST2FPC … #define CLK_INFRA_AO_DEVICE_APC_SYNC … #define CLK_INFRA_AO_PCIE_P1_PERI_26M … #define CLK_INFRA_AO_SPIS0 … #define CLK_INFRA_AO_SPIS1 … #define CLK_INFRA_AO_133M_M_PERI … #define CLK_INFRA_AO_66M_M_PERI … #define CLK_INFRA_AO_PCIE_PL_P_250M_P0 … #define CLK_INFRA_AO_PCIE_PL_P_250M_P1 … #define CLK_INFRA_AO_PCIE_P1_TL_96M … #define CLK_INFRA_AO_AES_MSDCFDE_0P … #define CLK_INFRA_AO_UFS_TX_SYMBOL … #define CLK_INFRA_AO_UFS_RX_SYMBOL … #define CLK_INFRA_AO_UFS_RX_SYMBOL1 … #define CLK_INFRA_AO_PERI_UFS_MEM_SUB … #define CLK_INFRA_AO_NR_CLK … /* APMIXEDSYS */ #define CLK_APMIXED_NNAPLL … #define CLK_APMIXED_RESPLL … #define CLK_APMIXED_ETHPLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_TVDPLL1 … #define CLK_APMIXED_TVDPLL2 … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_VDECPLL … #define CLK_APMIXED_IMGPLL … #define CLK_APMIXED_UNIVPLL … #define CLK_APMIXED_HDMIPLL1 … #define CLK_APMIXED_HDMIPLL2 … #define CLK_APMIXED_HDMIRX_APLL … #define CLK_APMIXED_USB1PLL … #define CLK_APMIXED_ADSPPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_APLL3 … #define CLK_APMIXED_APLL4 … #define CLK_APMIXED_APLL5 … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_DGIPLL … #define CLK_APMIXED_PLL_SSUSB26M … #define CLK_APMIXED_NR_CLK … /* SCP_ADSP */ #define CLK_SCP_ADSP_AUDIODSP … #define CLK_SCP_ADSP_NR_CLK … /* PERICFG_AO */ #define CLK_PERI_AO_ETHERNET … #define CLK_PERI_AO_ETHERNET_BUS … #define CLK_PERI_AO_FLASHIF_BUS … #define CLK_PERI_AO_FLASHIF_FLASH … #define CLK_PERI_AO_SSUSB_1P_BUS … #define CLK_PERI_AO_SSUSB_1P_XHCI … #define CLK_PERI_AO_SSUSB_2P_BUS … #define CLK_PERI_AO_SSUSB_2P_XHCI … #define CLK_PERI_AO_SSUSB_3P_BUS … #define CLK_PERI_AO_SSUSB_3P_XHCI … #define CLK_PERI_AO_SPINFI … #define CLK_PERI_AO_ETHERNET_MAC … #define CLK_PERI_AO_NFI_H … #define CLK_PERI_AO_FNFI1X … #define CLK_PERI_AO_PCIE_P0_MEM … #define CLK_PERI_AO_PCIE_P1_MEM … #define CLK_PERI_AO_NR_CLK … /* IMP_IIC_WRAP_S */ #define CLK_IMP_IIC_WRAP_S_I2C5 … #define CLK_IMP_IIC_WRAP_S_I2C6 … #define CLK_IMP_IIC_WRAP_S_I2C7 … #define CLK_IMP_IIC_WRAP_S_NR_CLK … /* IMP_IIC_WRAP_W */ #define CLK_IMP_IIC_WRAP_W_I2C0 … #define CLK_IMP_IIC_WRAP_W_I2C1 … #define CLK_IMP_IIC_WRAP_W_I2C2 … #define CLK_IMP_IIC_WRAP_W_I2C3 … #define CLK_IMP_IIC_WRAP_W_I2C4 … #define CLK_IMP_IIC_WRAP_W_NR_CLK … /* MFGCFG */ #define CLK_MFG_BG3D … #define CLK_MFG_NR_CLK … /* VPPSYS0 */ #define CLK_VPP0_MDP_FG … #define CLK_VPP0_STITCH … #define CLK_VPP0_PADDING … #define CLK_VPP0_MDP_TCC … #define CLK_VPP0_WARP0_ASYNC_TX … #define CLK_VPP0_WARP1_ASYNC_TX … #define CLK_VPP0_MUTEX … #define CLK_VPP0_VPP02VPP1_RELAY … #define CLK_VPP0_VPP12VPP0_ASYNC … #define CLK_VPP0_MMSYSRAM_TOP … #define CLK_VPP0_MDP_AAL … #define CLK_VPP0_MDP_RSZ … #define CLK_VPP0_SMI_COMMON … #define CLK_VPP0_GALS_VDO0_LARB0 … #define CLK_VPP0_GALS_VDO0_LARB1 … #define CLK_VPP0_GALS_VENCSYS … #define CLK_VPP0_GALS_VENCSYS_CORE1 … #define CLK_VPP0_GALS_INFRA … #define CLK_VPP0_GALS_CAMSYS … #define CLK_VPP0_GALS_VPP1_LARB5 … #define CLK_VPP0_GALS_VPP1_LARB6 … #define CLK_VPP0_SMI_REORDER … #define CLK_VPP0_SMI_IOMMU … #define CLK_VPP0_GALS_IMGSYS_CAMSYS … #define CLK_VPP0_MDP_RDMA … #define CLK_VPP0_MDP_WROT … #define CLK_VPP0_GALS_EMI0_EMI1 … #define CLK_VPP0_SMI_SUB_COMMON_REORDER … #define CLK_VPP0_SMI_RSI … #define CLK_VPP0_SMI_COMMON_LARB4 … #define CLK_VPP0_GALS_VDEC_VDEC_CORE1 … #define CLK_VPP0_GALS_VPP1_WPE … #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 … #define CLK_VPP0_FAKE_ENG … #define CLK_VPP0_MDP_HDR … #define CLK_VPP0_MDP_TDSHP … #define CLK_VPP0_MDP_COLOR … #define CLK_VPP0_MDP_OVL … #define CLK_VPP0_WARP0_RELAY … #define CLK_VPP0_WARP0_MDP_DL_ASYNC … #define CLK_VPP0_WARP1_RELAY … #define CLK_VPP0_WARP1_MDP_DL_ASYNC … #define CLK_VPP0_NR_CLK … /* WPESYS */ #define CLK_WPE_VPP0 … #define CLK_WPE_VPP1 … #define CLK_WPE_SMI_LARB7 … #define CLK_WPE_SMI_LARB8 … #define CLK_WPE_EVENT_TX … #define CLK_WPE_SMI_LARB7_P … #define CLK_WPE_SMI_LARB8_P … #define CLK_WPE_NR_CLK … /* WPESYS_VPP0 */ #define CLK_WPE_VPP0_VECI … #define CLK_WPE_VPP0_VEC2I … #define CLK_WPE_VPP0_VEC3I … #define CLK_WPE_VPP0_WPEO … #define CLK_WPE_VPP0_MSKO … #define CLK_WPE_VPP0_VGEN … #define CLK_WPE_VPP0_EXT … #define CLK_WPE_VPP0_VFC … #define CLK_WPE_VPP0_CACH0_TOP … #define CLK_WPE_VPP0_CACH0_DMA … #define CLK_WPE_VPP0_CACH1_TOP … #define CLK_WPE_VPP0_CACH1_DMA … #define CLK_WPE_VPP0_CACH2_TOP … #define CLK_WPE_VPP0_CACH2_DMA … #define CLK_WPE_VPP0_CACH3_TOP … #define CLK_WPE_VPP0_CACH3_DMA … #define CLK_WPE_VPP0_PSP … #define CLK_WPE_VPP0_PSP2 … #define CLK_WPE_VPP0_SYNC … #define CLK_WPE_VPP0_C24 … #define CLK_WPE_VPP0_MDP_CROP … #define CLK_WPE_VPP0_ISP_CROP … #define CLK_WPE_VPP0_TOP … #define CLK_WPE_VPP0_NR_CLK … /* WPESYS_VPP1 */ #define CLK_WPE_VPP1_VECI … #define CLK_WPE_VPP1_VEC2I … #define CLK_WPE_VPP1_VEC3I … #define CLK_WPE_VPP1_WPEO … #define CLK_WPE_VPP1_MSKO … #define CLK_WPE_VPP1_VGEN … #define CLK_WPE_VPP1_EXT … #define CLK_WPE_VPP1_VFC … #define CLK_WPE_VPP1_CACH0_TOP … #define CLK_WPE_VPP1_CACH0_DMA … #define CLK_WPE_VPP1_CACH1_TOP … #define CLK_WPE_VPP1_CACH1_DMA … #define CLK_WPE_VPP1_CACH2_TOP … #define CLK_WPE_VPP1_CACH2_DMA … #define CLK_WPE_VPP1_CACH3_TOP … #define CLK_WPE_VPP1_CACH3_DMA … #define CLK_WPE_VPP1_PSP … #define CLK_WPE_VPP1_PSP2 … #define CLK_WPE_VPP1_SYNC … #define CLK_WPE_VPP1_C24 … #define CLK_WPE_VPP1_MDP_CROP … #define CLK_WPE_VPP1_ISP_CROP … #define CLK_WPE_VPP1_TOP … #define CLK_WPE_VPP1_NR_CLK … /* VPPSYS1 */ #define CLK_VPP1_SVPP1_MDP_OVL … #define CLK_VPP1_SVPP1_MDP_TCC … #define CLK_VPP1_SVPP1_MDP_WROT … #define CLK_VPP1_SVPP1_VPP_PAD … #define CLK_VPP1_SVPP2_MDP_WROT … #define CLK_VPP1_SVPP2_VPP_PAD … #define CLK_VPP1_SVPP3_MDP_WROT … #define CLK_VPP1_SVPP3_VPP_PAD … #define CLK_VPP1_SVPP1_MDP_RDMA … #define CLK_VPP1_SVPP1_MDP_FG … #define CLK_VPP1_SVPP2_MDP_RDMA … #define CLK_VPP1_SVPP2_MDP_FG … #define CLK_VPP1_SVPP3_MDP_RDMA … #define CLK_VPP1_SVPP3_MDP_FG … #define CLK_VPP1_VPP_SPLIT … #define CLK_VPP1_SVPP2_VDO0_DL_RELAY … #define CLK_VPP1_SVPP1_MDP_TDSHP … #define CLK_VPP1_SVPP1_MDP_COLOR … #define CLK_VPP1_SVPP3_VDO1_DL_RELAY … #define CLK_VPP1_SVPP2_VPP_MERGE … #define CLK_VPP1_SVPP2_MDP_COLOR … #define CLK_VPP1_VPPSYS1_GALS … #define CLK_VPP1_SVPP3_VPP_MERGE … #define CLK_VPP1_SVPP3_MDP_COLOR … #define CLK_VPP1_VPPSYS1_LARB … #define CLK_VPP1_SVPP1_MDP_RSZ … #define CLK_VPP1_SVPP1_MDP_HDR … #define CLK_VPP1_SVPP1_MDP_AAL … #define CLK_VPP1_SVPP2_MDP_HDR … #define CLK_VPP1_SVPP2_MDP_AAL … #define CLK_VPP1_DL_ASYNC … #define CLK_VPP1_LARB5_FAKE_ENG … #define CLK_VPP1_SVPP3_MDP_HDR … #define CLK_VPP1_SVPP3_MDP_AAL … #define CLK_VPP1_SVPP2_VDO1_DL_RELAY … #define CLK_VPP1_LARB6_FAKE_ENG … #define CLK_VPP1_SVPP2_MDP_RSZ … #define CLK_VPP1_SVPP3_MDP_RSZ … #define CLK_VPP1_SVPP3_VDO0_DL_RELAY … #define CLK_VPP1_DISP_MUTEX … #define CLK_VPP1_SVPP2_MDP_TDSHP … #define CLK_VPP1_SVPP3_MDP_TDSHP … #define CLK_VPP1_VPP0_DL1_RELAY … #define CLK_VPP1_HDMI_META … #define CLK_VPP1_VPP_SPLIT_HDMI … #define CLK_VPP1_DGI_IN … #define CLK_VPP1_DGI_OUT … #define CLK_VPP1_VPP_SPLIT_DGI … #define CLK_VPP1_VPP0_DL_ASYNC … #define CLK_VPP1_VPP0_DL_RELAY … #define CLK_VPP1_VPP_SPLIT_26M … #define CLK_VPP1_NR_CLK … /* IMGSYS */ #define CLK_IMG_LARB9 … #define CLK_IMG_TRAW0 … #define CLK_IMG_TRAW1 … #define CLK_IMG_TRAW2 … #define CLK_IMG_TRAW3 … #define CLK_IMG_DIP0 … #define CLK_IMG_WPE0 … #define CLK_IMG_IPE … #define CLK_IMG_DIP1 … #define CLK_IMG_WPE1 … #define CLK_IMG_GALS … #define CLK_IMG_NR_CLK … /* IMGSYS1_DIP_TOP */ #define CLK_IMG1_DIP_TOP_LARB10 … #define CLK_IMG1_DIP_TOP_DIP_TOP … #define CLK_IMG1_DIP_TOP_NR_CLK … /* IMGSYS1_DIP_NR */ #define CLK_IMG1_DIP_NR_RESERVE … #define CLK_IMG1_DIP_NR_DIP_NR … #define CLK_IMG1_DIP_NR_NR_CLK … /* IMGSYS1_WPE */ #define CLK_IMG1_WPE_LARB11 … #define CLK_IMG1_WPE_WPE … #define CLK_IMG1_WPE_NR_CLK … /* IPESYS */ #define CLK_IPE_DPE … #define CLK_IPE_FDVT … #define CLK_IPE_ME … #define CLK_IPE_TOP … #define CLK_IPE_SMI_LARB12 … #define CLK_IPE_NR_CLK … /* CAMSYS */ #define CLK_CAM_LARB13 … #define CLK_CAM_LARB14 … #define CLK_CAM_MAIN_CAM … #define CLK_CAM_MAIN_CAMTG … #define CLK_CAM_SENINF … #define CLK_CAM_GCAMSVA … #define CLK_CAM_GCAMSVB … #define CLK_CAM_GCAMSVC … #define CLK_CAM_SCAMSA … #define CLK_CAM_SCAMSB … #define CLK_CAM_CAMSV_TOP … #define CLK_CAM_CAMSV_CQ … #define CLK_CAM_ADL … #define CLK_CAM_ASG … #define CLK_CAM_PDA … #define CLK_CAM_FAKE_ENG … #define CLK_CAM_MAIN_MRAW0 … #define CLK_CAM_MAIN_MRAW1 … #define CLK_CAM_MAIN_MRAW2 … #define CLK_CAM_MAIN_MRAW3 … #define CLK_CAM_CAM2MM0_GALS … #define CLK_CAM_CAM2MM1_GALS … #define CLK_CAM_CAM2SYS_GALS … #define CLK_CAM_NR_CLK … /* CAMSYS_RAWA */ #define CLK_CAM_RAWA_LARBX … #define CLK_CAM_RAWA_CAM … #define CLK_CAM_RAWA_CAMTG … #define CLK_CAM_RAWA_NR_CLK … /* CAMSYS_YUVA */ #define CLK_CAM_YUVA_LARBX … #define CLK_CAM_YUVA_CAM … #define CLK_CAM_YUVA_CAMTG … #define CLK_CAM_YUVA_NR_CLK … /* CAMSYS_RAWB */ #define CLK_CAM_RAWB_LARBX … #define CLK_CAM_RAWB_CAM … #define CLK_CAM_RAWB_CAMTG … #define CLK_CAM_RAWB_NR_CLK … /* CAMSYS_YUVB */ #define CLK_CAM_YUVB_LARBX … #define CLK_CAM_YUVB_CAM … #define CLK_CAM_YUVB_CAMTG … #define CLK_CAM_YUVB_NR_CLK … /* CAMSYS_MRAW */ #define CLK_CAM_MRAW_LARBX … #define CLK_CAM_MRAW_CAMTG … #define CLK_CAM_MRAW_MRAW0 … #define CLK_CAM_MRAW_MRAW1 … #define CLK_CAM_MRAW_MRAW2 … #define CLK_CAM_MRAW_MRAW3 … #define CLK_CAM_MRAW_NR_CLK … /* CCUSYS */ #define CLK_CCU_LARB18 … #define CLK_CCU_AHB … #define CLK_CCU_CCU0 … #define CLK_CCU_CCU1 … #define CLK_CCU_NR_CLK … /* VDECSYS_SOC */ #define CLK_VDEC_SOC_LARB1 … #define CLK_VDEC_SOC_LAT … #define CLK_VDEC_SOC_VDEC … #define CLK_VDEC_SOC_NR_CLK … /* VDECSYS */ #define CLK_VDEC_LARB1 … #define CLK_VDEC_LAT … #define CLK_VDEC_VDEC … #define CLK_VDEC_NR_CLK … /* VDECSYS_CORE1 */ #define CLK_VDEC_CORE1_LARB1 … #define CLK_VDEC_CORE1_LAT … #define CLK_VDEC_CORE1_VDEC … #define CLK_VDEC_CORE1_NR_CLK … /* APUSYS_PLL */ #define CLK_APUSYS_PLL_APUPLL … #define CLK_APUSYS_PLL_NPUPLL … #define CLK_APUSYS_PLL_APUPLL1 … #define CLK_APUSYS_PLL_APUPLL2 … #define CLK_APUSYS_PLL_NR_CLK … /* VENCSYS */ #define CLK_VENC_LARB … #define CLK_VENC_VENC … #define CLK_VENC_JPGENC … #define CLK_VENC_JPGDEC … #define CLK_VENC_JPGDEC_C1 … #define CLK_VENC_GALS … #define CLK_VENC_NR_CLK … /* VENCSYS_CORE1 */ #define CLK_VENC_CORE1_LARB … #define CLK_VENC_CORE1_VENC … #define CLK_VENC_CORE1_JPGENC … #define CLK_VENC_CORE1_JPGDEC … #define CLK_VENC_CORE1_JPGDEC_C1 … #define CLK_VENC_CORE1_GALS … #define CLK_VENC_CORE1_NR_CLK … /* VDOSYS0 */ #define CLK_VDO0_DISP_OVL0 … #define CLK_VDO0_DISP_COLOR0 … #define CLK_VDO0_DISP_COLOR1 … #define CLK_VDO0_DISP_CCORR0 … #define CLK_VDO0_DISP_CCORR1 … #define CLK_VDO0_DISP_AAL0 … #define CLK_VDO0_DISP_AAL1 … #define CLK_VDO0_DISP_GAMMA0 … #define CLK_VDO0_DISP_GAMMA1 … #define CLK_VDO0_DISP_DITHER0 … #define CLK_VDO0_DISP_DITHER1 … #define CLK_VDO0_DISP_OVL1 … #define CLK_VDO0_DISP_WDMA0 … #define CLK_VDO0_DISP_WDMA1 … #define CLK_VDO0_DISP_RDMA0 … #define CLK_VDO0_DISP_RDMA1 … #define CLK_VDO0_DSI0 … #define CLK_VDO0_DSI1 … #define CLK_VDO0_DSC_WRAP0 … #define CLK_VDO0_VPP_MERGE0 … #define CLK_VDO0_DP_INTF0 … #define CLK_VDO0_DISP_MUTEX0 … #define CLK_VDO0_DISP_IL_ROT0 … #define CLK_VDO0_APB_BUS … #define CLK_VDO0_FAKE_ENG0 … #define CLK_VDO0_FAKE_ENG1 … #define CLK_VDO0_DL_ASYNC0 … #define CLK_VDO0_DL_ASYNC1 … #define CLK_VDO0_DL_ASYNC2 … #define CLK_VDO0_DL_ASYNC3 … #define CLK_VDO0_DL_ASYNC4 … #define CLK_VDO0_DISP_MONITOR0 … #define CLK_VDO0_DISP_MONITOR1 … #define CLK_VDO0_DISP_MONITOR2 … #define CLK_VDO0_DISP_MONITOR3 … #define CLK_VDO0_DISP_MONITOR4 … #define CLK_VDO0_SMI_GALS … #define CLK_VDO0_SMI_COMMON … #define CLK_VDO0_SMI_EMI … #define CLK_VDO0_SMI_IOMMU … #define CLK_VDO0_SMI_LARB … #define CLK_VDO0_SMI_RSI … #define CLK_VDO0_DSI0_DSI … #define CLK_VDO0_DSI1_DSI … #define CLK_VDO0_DP_INTF0_DP_INTF … #define CLK_VDO0_NR_CLK … /* VDOSYS1 */ #define CLK_VDO1_SMI_LARB2 … #define CLK_VDO1_SMI_LARB3 … #define CLK_VDO1_GALS … #define CLK_VDO1_FAKE_ENG0 … #define CLK_VDO1_FAKE_ENG … #define CLK_VDO1_MDP_RDMA0 … #define CLK_VDO1_MDP_RDMA1 … #define CLK_VDO1_MDP_RDMA2 … #define CLK_VDO1_MDP_RDMA3 … #define CLK_VDO1_VPP_MERGE0 … #define CLK_VDO1_VPP_MERGE1 … #define CLK_VDO1_VPP_MERGE2 … #define CLK_VDO1_VPP_MERGE3 … #define CLK_VDO1_VPP_MERGE4 … #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC … #define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC … #define CLK_VDO1_DISP_MUTEX … #define CLK_VDO1_MDP_RDMA4 … #define CLK_VDO1_MDP_RDMA5 … #define CLK_VDO1_MDP_RDMA6 … #define CLK_VDO1_MDP_RDMA7 … #define CLK_VDO1_DP_INTF0_MM … #define CLK_VDO1_DPI0_MM … #define CLK_VDO1_DPI1_MM … #define CLK_VDO1_DISP_MONITOR … #define CLK_VDO1_MERGE0_DL_ASYNC … #define CLK_VDO1_MERGE1_DL_ASYNC … #define CLK_VDO1_MERGE2_DL_ASYNC … #define CLK_VDO1_MERGE3_DL_ASYNC … #define CLK_VDO1_MERGE4_DL_ASYNC … #define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC … #define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC … #define CLK_VDO1_HDR_VDO_FE0 … #define CLK_VDO1_HDR_GFX_FE0 … #define CLK_VDO1_HDR_VDO_BE … #define CLK_VDO1_HDR_VDO_FE1 … #define CLK_VDO1_HDR_GFX_FE1 … #define CLK_VDO1_DISP_MIXER … #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC … #define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC … #define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC … #define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC … #define CLK_VDO1_HDR_VDO_BE_DL_ASYNC … #define CLK_VDO1_DPI0 … #define CLK_VDO1_DISP_MONITOR_DPI0 … #define CLK_VDO1_DPI1 … #define CLK_VDO1_DISP_MONITOR_DPI1 … #define CLK_VDO1_DPINTF … #define CLK_VDO1_DISP_MONITOR_DPINTF … #define CLK_VDO1_26M_SLOW … #define CLK_VDO1_DPI1_HDMI … #define CLK_VDO1_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8195_H */
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