mt8195-resets.h | Explore in Territory

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
/*
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Christine Zhu <[email protected]>
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
#define _DT_BINDINGS_RESET_CONTROLLER_MT8195

/* TOPRGU resets */
#define MT8195_TOPRGU_CONN_MCU_SW_RST …
#define MT8195_TOPRGU_INFRA_GRST_SW_RST …
#define MT8195_TOPRGU_APU_SW_RST …
#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST …
#define MT8195_TOPRGU_MMSYS_SW_RST …
#define MT8195_TOPRGU_MFG_SW_RST …
#define MT8195_TOPRGU_VENC_SW_RST …
#define MT8195_TOPRGU_VDEC_SW_RST …
#define MT8195_TOPRGU_IMG_SW_RST …
#define MT8195_TOPRGU_APMIXEDSYS_SW_RST …
#define MT8195_TOPRGU_AUDIO_SW_RST …
#define MT8195_TOPRGU_CAMSYS_SW_RST …
#define MT8195_TOPRGU_EDPTX_SW_RST …
#define MT8195_TOPRGU_ADSPSYS_SW_RST …
#define MT8195_TOPRGU_DPTX_SW_RST …
#define MT8195_TOPRGU_SPMI_MST_SW_RST …

#define MT8195_TOPRGU_SW_RST_NUM …

/* INFRA resets */
#define MT8195_INFRA_RST0_THERM_CTRL_SWRST …
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST …
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST …
#define MT8195_INFRA_RST2_PCIE_P0_SWRST …
#define MT8195_INFRA_RST2_PCIE_P1_SWRST …
#define MT8195_INFRA_RST2_USBSIF_P1_SWRST …

/* VDOSYS1 */
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 …
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 …
#define MT8195_VDOSYS1_SW0_RST_B_GALS …
#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 …
#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 …
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 …
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 …
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 …
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 …
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 …
#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 …
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 …
#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 …
#define MT8195_VDOSYS1_SW0_RST_B_DPI0 …
#define MT8195_VDOSYS1_SW0_RST_B_DPI1 …
#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR …
#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC …
#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 …
#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC …
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC …

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
linux/include/dt-bindings/reset/mt8195-resets.h
