#ifndef __R8192UDM_H__
#define __R8192UDM_H__
#define OFDM_TABLE_LEN …
#define CCK_TABLE_LEN …
#define DM_DIG_THRESH_HIGH …
#define DM_DIG_THRESH_LOW …
#define DM_DIG_HIGH_PWR_THRESH_HIGH …
#define DM_DIG_HIGH_PWR_THRESH_LOW …
#define BW_AUTO_SWITCH_HIGH_LOW …
#define BW_AUTO_SWITCH_LOW_HIGH …
#define DM_DIG_BACKOFF …
#define DM_DIG_MAX …
#define DM_DIG_MIN …
#define DM_DIG_MIN_Netcore …
#define RX_PATH_SEL_SS_TH_LOW …
#define RX_PATH_SEL_DIFF_TH …
#define RATE_ADAPTIVE_TH_HIGH …
#define RATE_ADAPTIVE_TH_LOW_20M …
#define RATE_ADAPTIVE_TH_LOW_40M …
#define VERY_LOW_RSSI …
#define E_FOR_TX_POWER_TRACK …
#define TX_POWER_NEAR_FIELD_THRESH_HIGH …
#define TX_POWER_NEAR_FIELD_THRESH_LOW …
#define TX_POWER_ATHEROAP_THRESH_HIGH …
#define TX_POWER_ATHEROAP_THRESH_LOW …
#define CURRENT_TX_RATE_REG …
#define INITIAL_TX_RATE_REG …
#define TX_RETRY_COUNT_REG …
#define REG_C38_TH …
struct dig_t { … };
enum dm_ratr_sta { … };
enum dm_dig_connect { … };
enum dm_dig_pd_th { … };
enum dm_dig_cs_ratio { … };
struct drx_path_sel { … };
enum dm_cck_rx_path_method { … };
struct dcmd_txcmd { … };
extern struct dig_t dm_digtable;
extern const u32 dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN];
extern const u8 dm_cck_tx_bb_gain[CCK_TX_BB_GAIN_TABLE_LEN][8];
extern const u8 dm_cck_tx_bb_gain_ch14[CCK_TX_BB_GAIN_TABLE_LEN][8];
void rtl92e_dm_init(struct net_device *dev);
void rtl92e_dm_deinit(struct net_device *dev);
void rtl92e_dm_watchdog(struct net_device *dev);
void rtl92e_init_adaptive_rate(struct net_device *dev);
void rtl92e_dm_txpower_tracking_wq(void *data);
void rtl92e_dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
void rtl92e_dm_init_edca_turbo(struct net_device *dev);
void rtl92e_dm_rf_pathcheck_wq(void *data);
void rtl92e_dm_init_txpower_tracking(struct net_device *dev);
#endif