linux/drivers/clk/mediatek/clk-mt8195-apusys_pll.c

// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>

#include "clk-mtk.h"
#include "clk-pll.h"

#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#define MT8195_PLL_FMAX …
#define MT8195_PLL_FMIN …
#define MT8195_INTEGER_BITS …
#define MT8195_PCW_BITS …
#define MT8195_POSDIV_SHIFT …
#define MT8195_PLL_EN_BIT …
#define MT8195_PCW_SHIFT …

/*
 * The "en_reg" and "pcw_chg_reg" fields are standard offset register compared
 * with "reg" field, so set zero to imply it.
 * No tuner control in apu pll, so set "tuner_XXX" as zero to imply it.
 * No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
 * as zero to imply it.
 */
#define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) …

static const struct mtk_pll_data apusys_plls[] = …;

static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
{ … }

static void clk_mt8195_apusys_pll_remove(struct platform_device *pdev)
{ … }

static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apusys_pll);

static struct platform_driver clk_mt8195_apusys_pll_drv = …;
module_platform_driver(…) …;

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;