clk-mt8195-topckgen.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>

#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"

#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>

static DEFINE_SPINLOCK(mt8195_clk_lock);

static const struct mtk_fixed_clk top_fixed_clks[] = …;

static const struct mtk_fixed_factor top_divs[] = …;

static const char * const axi_parents[] = …;

static const char * const spm_parents[] = …;

static const char * const scp_parents[] = …;

static const char * const bus_aximem_parents[] = …;

static const char * const vpp_parents[] = …;

static const char * const ethdr_parents[] = …;

static const char * const ipe_parents[] = …;

static const char * const cam_parents[] = …;

static const char * const ccu_parents[] = …;

static const char * const img_parents[] = …;

static const char * const camtm_parents[] = …;

static const char * const dsp_parents[] = …;

static const char * const dsp1_parents[] = …;

static const char * const dsp2_parents[] = …;

static const char * const ipu_if_parents[] = …;

/*
 * MFG can be also parented to "univpll_d6" and "univpll_d7":
 * these have been removed from the parents list to let us
 * achieve GPU DVFS without any special clock handlers.
 */
static const char * const mfg_parents[] = …;

static const char * const camtg_parents[] = …;

static const char * const uart_parents[] = …;

static const char * const spi_parents[] = …;

static const char * const spis_parents[] = …;

static const char * const msdc50_0_h_parents[] = …;

static const char * const msdc50_0_parents[] = …;

static const char * const msdc30_parents[] = …;

static const char * const intdir_parents[] = …;

static const char * const aud_intbus_parents[] = …;

static const char * const audio_h_parents[] = …;

static const char * const pwrap_ulposc_parents[] = …;

static const char * const atb_parents[] = …;

static const char * const pwrmcu_parents[] = …;

/*
 * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using
 * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate
 * in dual output case, which would lead to corruption of functionality loss.
 */
static const char * const dp_parents[] = …;
static const u8 dp_parents_idx[] = …;

static const char * const edp_parents[] = …;
static const u8 edp_parents_idx[] = …;

static const char * const disp_pwm_parents[] = …;

static const char * const usb_parents[] = …;

static const char * const i2c_parents[] = …;

static const char * const seninf_parents[] = …;

static const char * const gcpu_parents[] = …;

static const char * const dxcc_parents[] = …;

static const char * const dpmaif_parents[] = …;

static const char * const aes_fde_parents[] = …;

static const char * const ufs_parents[] = …;

static const char * const ufs_tick1us_parents[] = …;

static const char * const ufs_mp_sap_parents[] = …;

static const char * const venc_parents[] = …;

static const char * const vdec_parents[] = …;

static const char * const pwm_parents[] = …;

static const char * const mcupm_parents[] = …;

static const char * const spmi_parents[] = …;

static const char * const dvfsrc_parents[] = …;

static const char * const tl_parents[] = …;

static const char * const dsi_occ_parents[] = …;

static const char * const wpe_vpp_parents[] = …;

static const char * const hdcp_parents[] = …;

static const char * const hdcp_24m_parents[] = …;

static const char * const hd20_dacr_ref_parents[] = …;

static const char * const hd20_hdcp_c_parents[] = …;

static const char * const hdmi_xtal_parents[] = …;

static const char * const hdmi_apb_parents[] = …;

static const char * const snps_eth_250m_parents[] = …;

static const char * const snps_eth_62p4m_ptp_parents[] = …;

static const char * const snps_eth_50m_rmii_parents[] = …;

static const char * const dgi_out_parents[] = …;

static const char * const nna_parents[] = …;

static const char * const adsp_parents[] = …;

static const char * const asm_parents[] = …;

static const char * const apll1_parents[] = …;

static const char * const apll2_parents[] = …;

static const char * const apll3_parents[] = …;

static const char * const apll4_parents[] = …;

static const char * const apll5_parents[] = …;

static const char * const i2s_parents[] = …;

static const char * const a1sys_hp_parents[] = …;

static const char * const a2sys_parents[] = …;

static const char * const a3sys_parents[] = …;

static const char * const spinfi_b_parents[] = …;

static const char * const nfi1x_parents[] = …;

static const char * const ecc_parents[] = …;

static const char * const audio_local_bus_parents[] = …;

static const char * const spinor_parents[] = …;

static const char * const dvio_dgi_ref_parents[] = …;

static const char * const ulposc_parents[] = …;

static const char * const ulposc_core_parents[] = …;

static const char * const srck_parents[] = …;

static const char * const mfg_fast_parents[] = …;

static const struct mtk_mux top_mtk_muxes[] = …;

static const struct mtk_composite top_adj_divs[] = …;

static const struct mtk_gate_regs top0_cg_regs = …;

static const struct mtk_gate_regs top1_cg_regs = …;

#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag) …

#define GATE_TOP0(_id, _name, _parent, _shift) …

#define GATE_TOP1(_id, _name, _parent, _shift) …

static const struct mtk_gate top_clks[] = …;

static const struct of_device_id of_match_clk_mt8195_topck[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_topck);

/* Register mux notifier for MFG mux */
static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{ … }

static int clk_mt8195_topck_probe(struct platform_device *pdev)
{ … }

static void clk_mt8195_topck_remove(struct platform_device *pdev)
{ … }

static struct platform_driver clk_mt8195_topck_drv = …;
module_platform_driver(…) …;

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;
linux/drivers/clk/mediatek/clk-mt8195-topckgen.c
