/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. * ******************************************************************************/ #ifndef __HAL_COMMON_REG_H__ #define __HAL_COMMON_REG_H__ /* */ /* */ /* 0x0000h ~ 0x00FFh System Configuration */ /* */ /* */ #define REG_SYS_FUNC_EN … #define REG_APS_FSMCO … #define REG_SYS_CLKR … #define REG_9346CR … #define REG_SYS_EEPROM_CTRL … #define REG_RSV_CTRL … #define REG_RF_CTRL … #define REG_AFE_XTAL_CTRL … #define REG_MAC_PHY_CTRL … #define REG_EFUSE_CTRL … #define REG_EFUSE_TEST … #define REG_PWR_DATA … #define REG_GPIO_MUXCFG … #define REG_GPIO_INTM … #define REG_LEDCFG0 … #define REG_LEDCFG2 … #define REG_HSIMR … #define REG_GPIO_IO_SEL_2 … #define REG_MULTI_FUNC_CTRL … #define REG_MCUFWDL … #define REG_EFUSE_ACCESS … #define REG_SYS_CFG … #define REG_GPIO_OUTSTS … /* */ /* */ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ #define REG_CR … #define REG_PBP … #define REG_TRXDMA_CTRL … #define REG_TRXFF_BNDY … #define REG_HIMR … #define REG_HISR … #define REG_C2HEVT_MSG_NORMAL … #define REG_C2HEVT_CLEAR … #define REG_HMETFR … #define REG_HMEBOX_0 … /* */ /* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ #define REG_RQPN … #define REG_TDECTRL … #define REG_TXDMA_STATUS … #define REG_RQPN_NPQ … #define REG_AUTO_LLT … /* */ /* */ /* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define REG_RXDMA_AGG_PG_TH … #define REG_RXPKT_NUM … /* */ /* */ /* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ #define REG_TXPKT_EMPTY … #define REG_FWHW_TXQ_CTRL … #define REG_HWSEQ_CTRL … #define REG_SPEC_SIFS … #define REG_RL … #define REG_RRSR … #define REG_PKT_VO_VI_LIFE_TIME … #define REG_PKT_BE_BK_LIFE_TIME … #define REG_BAR_MODE_CTRL … #define REG_EARLY_MODE_CONTROL … #define REG_MACID_SLEEP … #define REG_NQOS_SEQ … /* */ /* */ /* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ #define REG_EDCA_VO_PARAM … #define REG_EDCA_VI_PARAM … #define REG_EDCA_BE_PARAM … #define REG_EDCA_BK_PARAM … #define REG_BCNTCFG … #define REG_SIFS_CTX … #define REG_SIFS_TRX … #define REG_TSFTR_SYN_OFFSET … #define REG_SLOT … #define REG_TXPAUSE … #define REG_RD_CTRL … /* */ /* Format for offset 540h-542h: */ /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ /* [7:4]: Reserved. */ /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ /* [23:20]: Reserved */ /* Description: */ /* | */ /* |<--Setup--|--Hold------------>| */ /* --------------|---------------------- */ /* | */ /* TBTT */ /* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ /* Described by Designer Tim and Bruce, 2011-01-14. */ /* */ #define REG_TBTT_PROHIBIT … #define REG_BCN_CTRL … #define REG_BCN_CTRL_1 … #define REG_DUAL_TSF_RST … #define REG_BCN_INTERVAL … #define REG_DRVERLYINT … #define REG_BCNDMATIM … #define REG_ATIMWND … #define REG_BCN_MAX_ERR … #define REG_RXTSF_OFFSET_CCK … #define REG_RXTSF_OFFSET_OFDM … #define REG_TSFTR … #define REG_ACMHWCTRL … /* */ /* */ /* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ #define REG_BWOPMODE … #define REG_TCR … #define REG_RCR … #define REG_RX_DRVINFO_SZ … #define REG_MACID … #define REG_BSSID … #define REG_MAR … #define REG_MAC_SPEC_SIFS … /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ #define REG_RESP_SIFS_CCK … #define REG_RESP_SIFS_OFDM … #define REG_ACKTO … /* */ /* Note: */ /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is */ /* always too small, but the WiFi TestPlan test by 25, 000 microseconds of NAV through sending */ /* CTS in the air. We must update this value greater than 25, 000 microseconds to pass the item. */ /* The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented */ /* by SD1 Scott. */ /* By Bruce, 2011-07-18. */ /* */ #define REG_NAV_UPPER … /* WMA, BA, CCX */ #define REG_RXERR_RPT … /* Security */ #define REG_CAMCMD … #define REG_CAMWRITE … #define REG_CAMREAD … #define REG_SECCFG … /* Power */ #define REG_RXFLTMAP0 … #define REG_RXFLTMAP1 … #define REG_RXFLTMAP2 … #define REG_BCN_PSR_RPT … /* */ /* */ /* Redifine 8192C register definition for compatibility */ /* */ /* */ /* TODO: use these definition when using REG_xxx naming rule. */ /* NOTE: DO NOT Remove these definition. Use later. */ #define EFUSE_CTRL … #define EFUSE_TEST … #define MSR … #define PBP … /* */ /* 9. Security Control Registers (Offset:) */ /* */ #define RWCAM … #define WCAMI … /* */ /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ /* */ #define HSISR_GPIO12_0_INT … #define HSISR_SPS_OCP_INT … #define HSISR_RON_INT … #define HSISR_PDNINT … #define HSISR_GPIO9_INT … /* */ /* Response Rate Set Register (offset 0x440, 24bits) */ /* */ #define RRSR_1M … #define RRSR_2M … #define RRSR_5_5M … #define RRSR_11M … #define RRSR_6M … #define RRSR_12M … #define RRSR_24M … #define RRSR_CCK_RATES … /* */ /* Rate Definition */ /* */ /* CCK */ #define RATE_1M … #define RATE_2M … #define RATE_5_5M … #define RATE_11M … /* OFDM */ #define RATE_6M … #define RATE_9M … #define RATE_12M … #define RATE_18M … #define RATE_24M … #define RATE_36M … #define RATE_48M … #define RATE_54M … /* ALL CCK Rate */ #define RATE_BITMAP_ALL … /* Only use CCK 1M rate for ACK */ #define RATE_RRSR_CCK_ONLY_1M … /* */ /* BW_OPMODE bits (Offset 0x603, 8bit) */ /* */ #define BW_OPMODE_20MHZ … /* */ /* CAM Config Setting (offset 0x680, 1 byte) */ /* */ #define CAM_VALID … #define CAM_CONTENT_COUNT … #define CAM_AES … #define TOTAL_CAM_ENTRY … #define CAM_WRITE … #define CAM_POLLINIG … /* */ /* 12. Host Interrupt Status Registers */ /* */ /* */ /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ /* */ #define RCR_APPFCS … #define RCR_APP_MIC … #define RCR_APP_ICV … #define RCR_APP_PHYST_RXFF … #define RCR_APP_BA_SSN … #define RCR_HTC_LOC_CTRL … #define RCR_AMF … #define RCR_ADF … #define RCR_ACRC32 … #define RCR_CBSSID_BCN … #define RCR_CBSSID_DATA … #define RCR_AB … #define RCR_AM … #define RCR_APM … /* */ /* */ /* 0x0000h ~ 0x00FFh System Configuration */ /* */ /* */ /* 2 SYS_FUNC_EN */ #define FEN_BBRSTB … #define FEN_BB_GLB_RSTn … #define FEN_DIO_PCIE … #define FEN_PCIEA … #define FEN_PPLL … #define FEN_CPUEN … #define FEN_ELDR … /* 2 APS_FSMCO */ #define EnPDN … /* 2 SYS_CLKR */ #define ANA8M … #define LOADER_CLK_EN … /* 2 9346CR /REG_SYS_EEPROM_CTRL */ #define BOOT_FROM_EEPROM … #define EEPROM_EN … /* 2 RF_CTRL */ #define RF_EN … #define RF_RSTB … #define RF_SDMRSTB … /* 2 EFUSE_TEST (For RTL8723 partially) */ #define EFUSE_SEL(x) … #define EFUSE_SEL_MASK … #define EFUSE_WIFI_SEL_0 … #define EFUSE_BT_SEL_0 … #define EFUSE_BT_SEL_1 … #define EFUSE_BT_SEL_2 … /* 2 8051FWDL */ /* 2 MCUFWDL */ #define MCUFWDL_RDY … #define FWDL_ChkSum_rpt … #define WINTINI_RDY … #define RAM_DL_SEL … /* 2 REG_SYS_CFG */ #define VENDOR_ID … #define RTL_ID … #define SPS_SEL … #define CHIP_VER_RTL_MASK … #define CHIP_VER_RTL_SHIFT … /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */ #define RF_RL_ID … /* */ /* */ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ /* 2 Function Enable Registers */ /* 2 CR */ #define HCI_TXDMA_EN … #define HCI_RXDMA_EN … #define TXDMA_EN … #define RXDMA_EN … #define PROTOCOL_EN … #define SCHEDULE_EN … #define MACTXEN … #define MACRXEN … #define ENSWBCN … #define ENSEC … #define CALTMR_EN … /* Network type */ #define _NETTYPE(x) … #define MASK_NETTYPE … #define NT_LINK_AD_HOC … #define NT_LINK_AP … /* 2 PBP - Page Size Register */ #define _PSRX(x) … #define _PSTX(x) … #define PBP_128 … /* 2 TX/RXDMA */ #define RXDMA_AGG_EN … /* For normal driver, 0x10C */ #define _TXDMA_HIQ_MAP(x) … #define _TXDMA_MGQ_MAP(x) … #define _TXDMA_BKQ_MAP(x) … #define _TXDMA_BEQ_MAP(x) … #define _TXDMA_VIQ_MAP(x) … #define _TXDMA_VOQ_MAP(x) … #define QUEUE_LOW … #define QUEUE_NORMAL … #define QUEUE_HIGH … /* */ /* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* 2 RQPN */ #define _HPQ(x) … #define _LPQ(x) … #define _PUBQ(x) … #define _NPQ(x) … #define LD_RQPN … /* 2 AUTO_LLT */ #define BIT_AUTO_INIT_LLT … /* */ /* */ /* 0x0280h ~ 0x028Bh RX DMA Configuration */ /* */ /* */ /* 2 REG_RXDMA_CONTROL, 0x0286h */ /* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */ /* this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */ /* define RXPKT_RELEASE_POLL BIT(0) */ /* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */ /* this bit. FW can start releasing packets after RXDMA entering idle mode. */ /* define RXDMA_IDLE BIT(1) */ /* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */ /* completed, and stop DMA packet to host. RXDMA will then report Default: 0; */ /* define RW_RELEASE_EN BIT(2) */ /* 2 REG_RXPKT_NUM, 0x0284 */ #define RXPKT_RELEASE_POLL … #define RXDMA_IDLE … #define RW_RELEASE_EN … /* */ /* */ /* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ /* 2 FWHW_TXQ_CTRL */ #define EN_AMPDU_RTY_NEW … /* 2 SPEC SIFS */ #define _SPEC_SIFS_CCK(x) … #define _SPEC_SIFS_OFDM(x) … /* 2 RL */ #define RETRY_LIMIT_SHORT_SHIFT … #define RETRY_LIMIT_LONG_SHIFT … /* */ /* */ /* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ #define _LRL(x) … #define _SRL(x) … /* 2 BCN_CTRL */ #define EN_TXBCN_RPT … #define EN_BCN_FUNCTION … #define DIS_ATIM … #define DIS_BCNQ_SUB … #define DIS_TSF_UDT … /* 2 ACMHWCTRL */ #define AcmHw_HwEn … #define AcmHw_BeqEn … #define AcmHw_ViqEn … #define AcmHw_VoqEn … /* */ /* */ /* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ /* 2 TCR */ #define TSFRST … /* 2 RCR */ #define AB … /* 2 SECCFG */ #define SCR_TxUseDK … #define SCR_RxUseDK … #define SCR_TxEncEnable … #define SCR_RxDecEnable … #define SCR_TXBCUSEDK … #define SCR_RXBCUSEDK … #define SCR_CHK_KEYID … /* */ /* */ /* SDIO Bus Specification */ /* */ /* */ /* I/O bus domain address mapping */ #define SDIO_LOCAL_BASE … /* SDIO host local register space mapping. */ #define SDIO_LOCAL_MSK … #define WLAN_IOREG_MSK … #define WLAN_FIFO_MSK … #define WLAN_RX0FF_MSK … #define SDIO_LOCAL_DEVICE_ID … #define WLAN_TX_HIQ_DEVICE_ID … #define WLAN_TX_MIQ_DEVICE_ID … #define WLAN_TX_LOQ_DEVICE_ID … #define WLAN_RX0FF_DEVICE_ID … #define WLAN_IOREG_DEVICE_ID … /* SDIO Tx Free Page Index */ #define HI_QUEUE_IDX … #define MID_QUEUE_IDX … #define LOW_QUEUE_IDX … #define PUBLIC_QUEUE_IDX … #define SDIO_MAX_TX_QUEUE … #define SDIO_REG_TX_CTRL … #define SDIO_REG_HIMR … #define SDIO_REG_HISR … #define SDIO_REG_RX0_REQ_LEN … #define SDIO_REG_OQT_FREE_PG … #define SDIO_REG_FREE_TXPG … #define SDIO_REG_HRPWM1 … #define SDIO_REG_HSUS_CTRL … #define SDIO_HIMR_DISABLED … /* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */ #define SDIO_HIMR_RX_REQUEST_MSK … #define SDIO_HIMR_AVAL_MSK … /* SDIO Host Interrupt Service Routine */ #define SDIO_HISR_RX_REQUEST … #define SDIO_HISR_AVAL … #define SDIO_HISR_TXERR … #define SDIO_HISR_RXERR … #define SDIO_HISR_TXFOVW … #define SDIO_HISR_RXFOVW … #define SDIO_HISR_TXBCNOK … #define SDIO_HISR_TXBCNERR … #define SDIO_HISR_C2HCMD … #define SDIO_HISR_CPWM1 … #define SDIO_HISR_CPWM2 … #define SDIO_HISR_HSISR_IND … #define SDIO_HISR_GTINT3_IND … #define SDIO_HISR_GTINT4_IND … #define SDIO_HISR_PSTIMEOUT … #define SDIO_HISR_OCPINT … #define MASK_SDIO_HISR_CLEAR … /* SDIO Tx FIFO related */ #define SDIO_TX_FREE_PG_QUEUE … /* */ /* */ /* 0xFE00h ~ 0xFE55h USB Configuration */ /* */ /* */ /* 2REG_C2HEVT_CLEAR */ #define C2H_EVT_HOST_CLOSE … #define C2H_EVT_FW_CLOSE … /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ #define WL_HWPDN_SL … #define WL_FUNC_EN … #define BT_FUNC_EN … #define GPS_FUNC_EN … #endif /* __HAL_COMMON_H__ */
Codebase Browser
linux