linux/drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h

/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 *
 ******************************************************************************/

#ifndef	__ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__


/* 2 RF REG LIST */
#define ODM_REG_RF_MODE_11N
#define ODM_REG_RF_0B_11N
#define ODM_REG_CHNBW_11N
#define ODM_REG_T_METER_11N
#define ODM_REG_RF_25_11N
#define ODM_REG_RF_26_11N
#define ODM_REG_RF_27_11N
#define ODM_REG_RF_2B_11N
#define ODM_REG_RF_2C_11N
#define ODM_REG_RXRF_A3_11N
#define ODM_REG_T_METER_92D_11N
#define ODM_REG_T_METER_88E_11N

/* 2 BB REG LIST */
/* PAGE 8 */
#define ODM_REG_BB_CTRL_11N
#define ODM_REG_RF_PIN_11N
#define ODM_REG_PSD_CTRL_11N
#define ODM_REG_TX_ANT_CTRL_11N
#define ODM_REG_BB_PWR_SAV5_11N
#define ODM_REG_CCK_RPT_FORMAT_11N
#define ODM_REG_RX_DEFAULT_A_11N
#define ODM_REG_RX_DEFAULT_B_11N
#define ODM_REG_BB_PWR_SAV3_11N
#define ODM_REG_ANTSEL_CTRL_11N
#define ODM_REG_RX_ANT_CTRL_11N
#define ODM_REG_PIN_CTRL_11N
#define ODM_REG_BB_PWR_SAV1_11N
#define ODM_REG_ANTSEL_PATH_11N
#define ODM_REG_BB_3WIRE_11N
#define ODM_REG_SC_CNT_11N
#define ODM_REG_PSD_DATA_11N
#define ODM_REG_PSD_DATA_11N
#define ODM_REG_NHM_TIMER_11N
#define ODM_REG_NHM_TH9_TH10_11N
#define ODM_REG_NHM_TH3_TO_TH0_11N
#define ODM_REG_NHM_TH7_TO_TH4_11N
#define ODM_REG_NHM_CNT_11N
/* PAGE 9 */
#define ODM_REG_DBG_RPT_11N
#define ODM_REG_ANT_MAPPING1_11N
#define ODM_REG_ANT_MAPPING2_11N
/* PAGE A */
#define ODM_REG_CCK_ANTDIV_PARA1_11N
#define ODM_REG_CCK_CCA_11N
#define ODM_REG_CCK_ANTDIV_PARA2_11N
#define ODM_REG_CCK_ANTDIV_PARA3_11N
#define ODM_REG_CCK_ANTDIV_PARA4_11N
#define ODM_REG_CCK_FILTER_PARA1_11N
#define ODM_REG_CCK_FILTER_PARA2_11N
#define ODM_REG_CCK_FILTER_PARA3_11N
#define ODM_REG_CCK_FILTER_PARA4_11N
#define ODM_REG_CCK_FILTER_PARA5_11N
#define ODM_REG_CCK_FILTER_PARA6_11N
#define ODM_REG_CCK_FILTER_PARA7_11N
#define ODM_REG_CCK_FILTER_PARA8_11N
#define ODM_REG_CCK_FA_RST_11N
#define ODM_REG_CCK_FA_MSB_11N
#define ODM_REG_CCK_FA_LSB_11N
#define ODM_REG_CCK_CCA_CNT_11N
#define ODM_REG_BB_PWR_SAV4_11N
/* PAGE B */
#define ODM_REG_LNA_SWITCH_11N
#define ODM_REG_PATH_SWITCH_11N
#define ODM_REG_RSSI_CTRL_11N
#define ODM_REG_CONFIG_ANTA_11N
#define ODM_REG_RSSI_BT_11N
/* PAGE C */
#define ODM_REG_OFDM_FA_HOLDC_11N
#define ODM_REG_BB_RX_PATH_11N
#define ODM_REG_TRMUX_11N
#define ODM_REG_OFDM_FA_RSTC_11N
#define ODM_REG_RXIQI_MATRIX_11N
#define ODM_REG_TXIQK_MATRIX_LSB1_11N
#define ODM_REG_IGI_A_11N
#define ODM_REG_ANTDIV_PARA2_11N
#define ODM_REG_IGI_B_11N
#define ODM_REG_ANTDIV_PARA3_11N
#define ODM_REG_L1SBD_PD_CH_11N
#define ODM_REG_BB_PWR_SAV2_11N
#define ODM_REG_RX_OFF_11N
#define ODM_REG_TXIQK_MATRIXA_11N
#define ODM_REG_TXIQK_MATRIXB_11N
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N
#define ODM_REG_RXIQK_MATRIX_LSB_11N
#define ODM_REG_ANTDIV_PARA1_11N
#define ODM_REG_OFDM_FA_TYPE1_11N
/* PAGE D */
#define ODM_REG_OFDM_FA_RSTD_11N
#define ODM_REG_BB_ATC_11N
#define ODM_REG_OFDM_FA_TYPE2_11N
#define ODM_REG_OFDM_FA_TYPE3_11N
#define ODM_REG_OFDM_FA_TYPE4_11N
#define ODM_REG_RPT_11N
/* PAGE E */
#define ODM_REG_TXAGC_A_6_18_11N
#define ODM_REG_TXAGC_A_24_54_11N
#define ODM_REG_TXAGC_A_1_MCS32_11N
#define ODM_REG_TXAGC_A_MCS0_3_11N
#define ODM_REG_TXAGC_A_MCS4_7_11N
#define ODM_REG_FPGA0_IQK_11N
#define ODM_REG_TXIQK_TONE_A_11N
#define ODM_REG_RXIQK_TONE_A_11N
#define ODM_REG_TXIQK_PI_A_11N
#define ODM_REG_RXIQK_PI_A_11N
#define ODM_REG_TXIQK_11N
#define ODM_REG_RXIQK_11N
#define ODM_REG_IQK_AGC_PTS_11N
#define ODM_REG_IQK_AGC_RSP_11N
#define ODM_REG_BLUETOOTH_11N
#define ODM_REG_RX_WAIT_CCA_11N
#define ODM_REG_TX_CCK_RFON_11N
#define ODM_REG_TX_CCK_BBON_11N
#define ODM_REG_OFDM_RFON_11N
#define ODM_REG_OFDM_BBON_11N
#define ODM_REG_TX2RX_11N
#define ODM_REG_TX2TX_11N
#define ODM_REG_RX_CCK_11N
#define ODM_REG_RX_OFDM_11N
#define ODM_REG_RX_WAIT_RIFS_11N
#define ODM_REG_RX2RX_11N
#define ODM_REG_STANDBY_11N
#define ODM_REG_SLEEP_11N
#define ODM_REG_PMPD_ANAEN_11N
#define ODM_REG_IGI_C_11N
#define ODM_REG_IGI_D_11N

/* 2 MAC REG LIST */
#define ODM_REG_BB_RST_11N
#define ODM_REG_ANTSEL_PIN_11N
#define ODM_REG_EARLY_MODE_11N
#define ODM_REG_RSSI_MONITOR_11N
#define ODM_REG_EDCA_VO_11N
#define ODM_REG_EDCA_VI_11N
#define ODM_REG_EDCA_BE_11N
#define ODM_REG_EDCA_BK_11N
#define ODM_REG_TXPAUSE_11N
#define ODM_REG_RESP_TX_11N
#define ODM_REG_ANT_TRAIN_PARA1_11N
#define ODM_REG_ANT_TRAIN_PARA2_11N


/* DIG Related */
#define ODM_BIT_IGI_11N
#define ODM_BIT_CCK_RPT_FORMAT_11N
#define ODM_BIT_BB_RX_PATH_11N
#define ODM_BIT_BB_ATC_11N

#endif