/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. * *******************************************************************************/ #ifndef __RTL8723B_SPEC_H__ #define __RTL8723B_SPEC_H__ #define HAL_NAV_UPPER_UNIT_8723B … /* */ /* */ /* 0x0000h ~ 0x00FFh System Configuration */ /* */ /* */ #define REG_RSV_CTRL_8723B … #define REG_BT_WIFI_ANTENNA_SWITCH_8723B … #define REG_HSISR_8723B … #define REG_PAD_CTRL1_8723B … #define REG_AFE_CTRL_4_8723B … #define REG_HMEBOX_DBG_0_8723B … #define REG_HMEBOX_DBG_1_8723B … #define REG_HMEBOX_DBG_2_8723B … #define REG_HMEBOX_DBG_3_8723B … #define REG_HIMR0_8723B … #define REG_HISR0_8723B … #define REG_HIMR1_8723B … #define REG_HISR1_8723B … #define REG_PMC_DBG_CTRL2_8723B … /* */ /* */ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ #define REG_C2HEVT_CMD_ID_8723B … #define REG_C2HEVT_CMD_LEN_8723B … #define REG_WOWLAN_WAKE_REASON … #define REG_WOWLAN_GTK_DBG1 … #define REG_WOWLAN_GTK_DBG2 … #define REG_HMEBOX_EXT0_8723B … #define REG_HMEBOX_EXT1_8723B … #define REG_HMEBOX_EXT2_8723B … #define REG_HMEBOX_EXT3_8723B … /* */ /* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* */ /* */ /* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define REG_RXDMA_CONTROL_8723B … #define REG_RXDMA_MODE_CTRL_8723B … /* */ /* */ /* 0x0300h ~ 0x03FFh PCIe */ /* */ /* */ #define REG_PCIE_CTRL_REG_8723B … #define REG_INT_MIG_8723B … #define REG_BCNQ_DESA_8723B … #define REG_HQ_DESA_8723B … #define REG_MGQ_DESA_8723B … #define REG_VOQ_DESA_8723B … #define REG_VIQ_DESA_8723B … #define REG_BEQ_DESA_8723B … #define REG_BKQ_DESA_8723B … #define REG_RX_DESA_8723B … #define REG_DBI_WDATA_8723B … #define REG_DBI_RDATA_8723B … #define REG_DBI_ADDR_8723B … #define REG_DBI_FLAG_8723B … #define REG_MDIO_WDATA_8723B … #define REG_MDIO_RDATA_8723B … #define REG_MDIO_CTL_8723B … #define REG_DBG_SEL_8723B … #define REG_PCIE_HRPWM_8723B … #define REG_PCIE_HCPWM_8723B … #define REG_PCIE_MULTIFET_CTRL_8723B … /* */ /* */ /* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ #define REG_TXPKTBUF_BCNQ_BDNY_8723B … #define REG_TXPKTBUF_MGQ_BDNY_8723B … #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B … #define REG_AMPDU_BURST_MODE_8723B … /* */ /* */ /* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ #define REG_SECONDARY_CCA_CTRL_8723B … /* */ /* */ /* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ /* */ /* SDIO Bus Specification */ /* */ /* */ /* SDIO CMD Address Mapping */ /* */ /* */ /* I/O bus domain (Host) */ /* */ /* */ /* SDIO register */ /* */ #define SDIO_REG_HCPWM1_8723B … /* */ /* 8723 Register Bit and Content definition */ /* */ /* 2 HSISR */ /* interrupt mask which needs to clear */ #define MASK_HSISR_CLEAR … /* */ /* */ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ /* */ /* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* */ /* */ /* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define BIT_USB_RXDMA_AGG_EN … #define RXDMA_AGG_MODE_EN … /* */ /* */ /* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ /* */ /* 8723B REG_CCK_CHECK (offset 0x454) */ /* */ #define BIT_BCN_PORT_SEL … /* */ /* */ /* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ /* */ /* */ /* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ #define EEPROM_RF_GAIN_OFFSET … #define EEPROM_RF_GAIN_VAL … /* */ /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ /* */ #define IMR_DISABLED_8723B … /* IMR DW0(0x00B0-00B3) Bit 0-31 */ #define IMR_TIMER2_8723B … #define IMR_TIMER1_8723B … #define IMR_PSTIMEOUT_8723B … #define IMR_GTINT4_8723B … #define IMR_GTINT3_8723B … #define IMR_TXBCN0ERR_8723B … #define IMR_TXBCN0OK_8723B … #define IMR_TSF_BIT32_TOGGLE_8723B … #define IMR_BCNDMAINT0_8723B … #define IMR_BCNDERR0_8723B … #define IMR_HSISR_IND_ON_INT_8723B … #define IMR_BCNDMAINT_E_8723B … #define IMR_ATIMEND_8723B … #define IMR_C2HCMD_8723B … #define IMR_CPWM2_8723B … #define IMR_CPWM_8723B … #define IMR_HIGHDOK_8723B … #define IMR_MGNTDOK_8723B … #define IMR_BKDOK_8723B … #define IMR_BEDOK_8723B … #define IMR_VIDOK_8723B … #define IMR_VODOK_8723B … #define IMR_RDU_8723B … #define IMR_ROK_8723B … /* IMR DW1(0x00B4-00B7) Bit 0-31 */ #define IMR_BCNDMAINT7_8723B … #define IMR_BCNDMAINT6_8723B … #define IMR_BCNDMAINT5_8723B … #define IMR_BCNDMAINT4_8723B … #define IMR_BCNDMAINT3_8723B … #define IMR_BCNDMAINT2_8723B … #define IMR_BCNDMAINT1_8723B … #define IMR_BCNDOK7_8723B … #define IMR_BCNDOK6_8723B … #define IMR_BCNDOK5_8723B … #define IMR_BCNDOK4_8723B … #define IMR_BCNDOK3_8723B … #define IMR_BCNDOK2_8723B … #define IMR_BCNDOK1_8723B … #define IMR_ATIMEND_E_8723B … #define IMR_TXERR_8723B … #define IMR_RXERR_8723B … #define IMR_TXFOVW_8723B … #define IMR_RXFOVW_8723B … #endif
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