/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. * ******************************************************************************/ #ifndef __HALPWRSEQCMD_H__ #define __HALPWRSEQCMD_H__ #include <drv_types.h> /*---------------------------------------------*/ /* 3 The value of cmd: 4 bits */ /*---------------------------------------------*/ #define PWR_CMD_READ … /* offset: the read register offset */ /* msk: the mask of the read value */ /* value: N/A, left by 0 */ /* note: dirver shall implement this function by read & msk */ #define PWR_CMD_WRITE … /* offset: the read register offset */ /* msk: the mask of the write bits */ /* value: write value */ /* note: driver shall implement this cmd by read & msk after write */ #define PWR_CMD_POLLING … /* offset: the read register offset */ /* msk: the mask of the polled value */ /* value: the value to be polled, masked by the msd field. */ /* note: driver shall implement this cmd by */ /* do{ */ /* if ((Read(offset) & msk) == (value & msk)) */ /* break; */ /* } while (not timeout); */ #define PWR_CMD_DELAY … /* offset: the value to delay */ /* msk: N/A */ /* value: the unit of delay, 0: us, 1: ms */ #define PWR_CMD_END … /* offset: N/A */ /* msk: N/A */ /* value: N/A */ /*---------------------------------------------*/ /* 3 The value of base: 4 bits */ /*---------------------------------------------*/ /* define the base address of each block */ #define PWR_BASEADDR_MAC … #define PWR_BASEADDR_SDIO … /*---------------------------------------------*/ /* 3 The value of interface_msk: 4 bits */ /*---------------------------------------------*/ #define PWR_INTF_SDIO_MSK … #define PWR_INTF_USB_MSK … #define PWR_INTF_PCI_MSK … #define PWR_INTF_ALL_MSK … /*---------------------------------------------*/ /* 3 The value of fab_msk: 4 bits */ /*---------------------------------------------*/ #define PWR_FAB_ALL_MSK … /*---------------------------------------------*/ /* 3 The value of cut_msk: 8 bits */ /*---------------------------------------------*/ #define PWR_CUT_TESTCHIP_MSK … #define PWR_CUT_ALL_MSK … enum { … }; struct wlan_pwr_cfg { … }; #define GET_PWR_CFG_OFFSET(__PWR_CMD) … #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) … #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) … #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) … #define GET_PWR_CFG_BASE(__PWR_CMD) … #define GET_PWR_CFG_CMD(__PWR_CMD) … #define GET_PWR_CFG_MASK(__PWR_CMD) … #define GET_PWR_CFG_VALUE(__PWR_CMD) … /* */ /* Prototype of protected function. */ /* */ u8 HalPwrSeqCmdParsing( struct adapter *padapter, u8 CutVersion, u8 FabVersion, u8 InterfaceType, struct wlan_pwr_cfg PwrCfgCmd[]); #endif
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