/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. * ******************************************************************************/ /***************************************************************************** * * Module: __INC_HAL8192CPHYREG_H * * * Note: 1. Define PMAC/BB register map * 2. Define RF register map * 3. PMAC/BB register bit mask. * 4. RF reg bit mask. * 5. Other BB/RF relative definition. * * * Export: Constants, macro, functions(API), global variables(None). * * Abbrev: * * History: * Data Who Remark * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. * 2. Reorganize code architecture. *09/25/2008 MH 1. Add RL6052 register definition * *****************************************************************************/ #ifndef __INC_HAL8192CPHYREG_H #define __INC_HAL8192CPHYREG_H /*--------------------------Define Parameters-------------------------------*/ /* */ /* 8192S Register offset definition */ /* */ /* */ /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ /* 3. RF register 0x00-2E */ /* 4. Bit Mask for BB/RF register */ /* 5. Other definition for BB/RF R/W */ /* */ /* */ /* 3. Page8(0x800) */ /* */ #define rFPGA0_RFMOD … #define rFPGA0_XA_HSSIParameter1 … #define rFPGA0_XA_HSSIParameter2 … #define rFPGA0_XB_HSSIParameter1 … #define rFPGA0_XB_HSSIParameter2 … #define rTxAGC_B_Rate18_06 … #define rTxAGC_B_Rate54_24 … #define rTxAGC_B_CCK1_55_Mcs32 … #define rTxAGC_B_Mcs03_Mcs00 … #define rTxAGC_B_Mcs07_Mcs04 … #define rFPGA0_XA_LSSIParameter … #define rFPGA0_XB_LSSIParameter … #define rFPGA0_XCD_SwitchControl … #define rFPGA0_XA_RFInterfaceOE … #define rFPGA0_XB_RFInterfaceOE … #define rTxAGC_B_CCK11_A_CCK2_11 … #define rFPGA0_XAB_RFInterfaceSW … #define rFPGA0_XCD_RFInterfaceSW … #define rFPGA0_XA_LSSIReadBack … #define rFPGA0_XB_LSSIReadBack … #define TransceiverA_HSPI_Readback … #define TransceiverB_HSPI_Readback … /* */ /* 4. Page9(0x900) */ /* */ #define rFPGA1_RFMOD … #define rS0S1_PathSwitch … /* */ /* 5. PageA(0xA00) */ /* */ /* Set Control channel to upper or lower. These settings are required only for 40MHz */ #define rCCK0_System … #define rCCK0_AFESetting … /* */ /* PageB(0xB00) */ /* */ #define rConfig_AntA … #define rConfig_AntB … /* */ /* 6. PageC(0xC00) */ /* */ #define rOFDM0_TRxPathEnable … #define rOFDM0_TRMuxPar … #define rOFDM0_XARxIQImbalance … #define rOFDM0_XBRxIQImbalance … #define rOFDM0_RxDSP … #define rOFDM0_ECCAThreshold … #define rOFDM0_AGCRSSITable … #define rOFDM0_XATxIQImbalance … #define rOFDM0_XBTxIQImbalance … #define rOFDM0_XCTxAFE … #define rOFDM0_XDTxAFE … #define rOFDM0_RxIQExtAnta … #define rOFDM0_TxPseudoNoiseWgt … /* */ /* 7. PageD(0xD00) */ /* */ #define rOFDM1_LSTF … /* */ /* 8. PageE(0xE00) */ /* */ #define rTxAGC_A_Rate18_06 … #define rTxAGC_A_Rate54_24 … #define rTxAGC_A_CCK1_Mcs32 … #define rTxAGC_A_Mcs03_Mcs00 … #define rTxAGC_A_Mcs07_Mcs04 … #define rFPGA0_IQK … #define rTx_IQK_Tone_A … #define rRx_IQK_Tone_A … #define rTx_IQK_PI_A … #define rRx_IQK_PI_A … #define rTx_IQK … #define rRx_IQK … #define rIQK_AGC_Pts … #define rIQK_AGC_Rsp … #define rTx_IQK_Tone_B … #define rRx_IQK_Tone_B … #define rTx_IQK_PI_B … #define rRx_IQK_PI_B … #define rBlue_Tooth … #define rRx_Wait_CCA … #define rTx_CCK_RFON … #define rTx_CCK_BBON … #define rTx_OFDM_RFON … #define rTx_OFDM_BBON … #define rTx_To_Rx … #define rTx_To_Tx … #define rRx_CCK … #define rTx_Power_Before_IQK_A … #define rTx_Power_After_IQK_A … #define rRx_Power_Before_IQK_A_2 … #define rRx_Power_After_IQK_A_2 … #define rRx_OFDM … #define rRx_Wait_RIFS … #define rRx_TO_Rx … #define rStandby … #define rSleep … #define rPMPD_ANAEN … /* */ /* RL6052 Register definition */ /* */ #define RF_AC … #define RF_TXM_IDAC … #define RF_CHNLBW … #define RF_RCK_OS … #define RF_TXPA_G1 … #define RF_TXPA_G2 … #define RF_WE_LUT … /* 2. Page8(0x800) */ #define bRFMOD … #define b3WireDataLength … #define b3WireAddressLength … #define bRFSI_RFENV … #define bLSSIReadAddress … #define bLSSIReadEdge … #define bLSSIReadBackData … /* 4. PageA(0xA00) */ #define bCCKSideBand … /* */ /* Other Definition */ /* */ /* for PutRegsetting & GetRegSetting BitMask */ #define bMaskByte0 … #define bMaskByte1 … #define bMaskByte2 … #define bMaskByte3 … #define bMaskHWord … #define bMaskLWord … #define bMaskDWord … #define bMaskH3Bytes … #define bMask12Bits … #define bMaskH4Bits … #define bEnable … #define rDPDT_control … #endif /* __INC_HAL8192SPHYREG_H */
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