linux/drivers/staging/rtl8723bs/hal/hal_com.c

// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 *
 ******************************************************************************/

#include <linux/kernel.h>
#include <drv_types.h>
#include <rtw_debug.h>
#include "hal_com_h2c.h"

#include "odm_precomp.h"

u8 rtw_hal_data_init(struct adapter *padapter)
{ … }

void rtw_hal_data_deinit(struct adapter *padapter)
{ … }


void dump_chip_info(struct hal_version	ChipVersion)
{ … }


#define EEPROM_CHANNEL_PLAN_BY_HW_MASK …

/*
 * Description:
 *Use hardware(efuse), driver parameter(registry) and default channel plan
 *to decide which one should be used.
 *
 * Parameters:
 *padapter			pointer of adapter
 *hw_channel_plan		channel plan from HW (efuse/eeprom)
 *					BIT[7] software configure mode; 0:Enable, 1:disable
 *					BIT[6:0] Channel Plan
 *sw_channel_plan		channel plan from SW (registry/module param)
 *def_channel_plan	channel plan used when HW/SW both invalid
 *AutoLoadFail		efuse autoload fail or not
 *
 * Return:
 *Final channel plan decision
 *
 */
u8 hal_com_config_channel_plan(
	struct adapter *padapter,
	u8 hw_channel_plan,
	u8 sw_channel_plan,
	u8 def_channel_plan,
	bool AutoLoadFail
)
{ … }

bool HAL_IsLegalChannel(struct adapter *adapter, u32 Channel)
{ … }

u8 MRateToHwRate(u8 rate)
{ … }

u8 HwRateToMRate(u8 rate)
{ … }

void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg)
{ … }

static void _OneOutPipeMapping(struct adapter *padapter)
{ … }

static void _TwoOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
{ … }

static void _ThreeOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
{ … }

bool Hal_MappingOutPipe(struct adapter *padapter, u8 NumOutPipe)
{ … }

void hal_init_macaddr(struct adapter *adapter)
{ … }

void rtw_init_hal_com_default_value(struct adapter *Adapter)
{ … }

/*
* C2H event format:
* Field	 TRIGGER		CONTENT	   CMD_SEQ	CMD_LEN		 CMD_ID
* BITS	 [127:120]	[119:16]      [15:8]		  [7:4]		   [3:0]
*/

void c2h_evt_clear(struct adapter *adapter)
{ … }

/*
* C2H event format:
* Field    TRIGGER    CMD_LEN    CONTENT    CMD_SEQ    CMD_ID
* BITS    [127:120]   [119:112]    [111:16]	     [15:8]         [7:0]
*/
s32 c2h_evt_read_88xx(struct adapter *adapter, u8 *buf)
{ … }

u8 rtw_get_mgntframe_raid(struct adapter *adapter, unsigned char network_type)
{ … }

void rtw_hal_update_sta_rate_mask(struct adapter *padapter, struct sta_info *psta)
{ … }

void hw_var_port_switch(struct adapter *adapter)
{ … }

void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
{ … }

void GetHwReg(struct adapter *adapter, u8 variable, u8 *val)
{ … }




u8 SetHalDefVar(
	struct adapter *adapter, enum hal_def_variable variable, void *value
)
{ … }

u8 GetHalDefVar(
	struct adapter *adapter, enum hal_def_variable variable, void *value
)
{ … }

void GetHalODMVar(
	struct adapter *Adapter,
	enum hal_odm_variable eVariable,
	void *pValue1,
	void *pValue2
)
{ … }

void SetHalODMVar(
	struct adapter *Adapter,
	enum hal_odm_variable eVariable,
	void *pValue1,
	bool bSet
)
{ … }


bool eqNByte(u8 *str1, u8 *str2, u32 num)
{ … }

bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
{ … }

void rtw_hal_check_rxfifo_full(struct adapter *adapter)
{ … }

#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
void rtw_dump_raw_rssi_info(struct adapter *padapter)
{
	u8 isCCKrate, rf_path;
	struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;

	isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;

	if (isCCKrate)
		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;

	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
		if (!isCCKrate) {
			printk(", rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
			psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
		} else {
			printk("\n");
		}
	}
}

void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe)
{
	u8 isCCKrate, rf_path;
	struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;

	struct odm_phy_info *pPhyInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;

	psample_pkt_rssi->data_rate = pattrib->data_rate;
	isCCKrate = pattrib->data_rate <= DESC_RATE11M;

	psample_pkt_rssi->pwdball = pPhyInfo->rx_pwd_ba11;
	psample_pkt_rssi->pwr_all = pPhyInfo->recv_signal_power;

	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
		psample_pkt_rssi->mimo_signal_strength[rf_path] = pPhyInfo->rx_mimo_signal_strength[rf_path];
		psample_pkt_rssi->mimo_signal_quality[rf_path] = pPhyInfo->rx_mimo_signal_quality[rf_path];
		if (!isCCKrate) {
			psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
			psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
		}
	}
}
#endif

static u32 Array_kfreemap[] = …;

void rtw_bb_rf_gain_offset(struct adapter *padapter)
{ … }