// SPDX-License-Identifier: GPL-2.0-or-later /* * AMD SoC Power Management Controller Driver * * Copyright (c) 2020, Advanced Micro Devices, Inc. * All Rights Reserved. * * Author: Shyam Sundar S K <[email protected]> */ #define pr_fmt(fmt) … #include <asm/amd_nb.h> #include <linux/acpi.h> #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/limits.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/rtc.h> #include <linux/serio.h> #include <linux/suspend.h> #include <linux/seq_file.h> #include <linux/uaccess.h> #include "pmc.h" /* SMU communication registers */ #define AMD_PMC_REGISTER_RESPONSE … #define AMD_PMC_REGISTER_ARGUMENT … /* PMC Scratch Registers */ #define AMD_PMC_SCRATCH_REG_CZN … #define AMD_PMC_SCRATCH_REG_YC … #define AMD_PMC_SCRATCH_REG_1AH … /* STB Registers */ #define AMD_PMC_STB_PMI_0 … #define AMD_PMC_STB_S2IDLE_PREPARE … #define AMD_PMC_STB_S2IDLE_RESTORE … #define AMD_PMC_STB_S2IDLE_CHECK … #define AMD_PMC_STB_DUMMY_PC … /* STB S2D(Spill to DRAM) has different message port offset */ #define AMD_S2D_REGISTER_MESSAGE … #define AMD_S2D_REGISTER_RESPONSE … #define AMD_S2D_REGISTER_ARGUMENT … /* STB Spill to DRAM Parameters */ #define S2D_TELEMETRY_BYTES_MAX … #define S2D_RSVD_RAM_SPACE … #define S2D_TELEMETRY_DRAMBYTES_MAX … /* STB Spill to DRAM Message Definition */ #define STB_FORCE_FLUSH_DATA … /* Base address of SMU for mapping physical address to virtual address */ #define AMD_PMC_MAPPING_SIZE … #define AMD_PMC_BASE_ADDR_OFFSET … #define AMD_PMC_BASE_ADDR_LO … #define AMD_PMC_BASE_ADDR_HI … #define AMD_PMC_BASE_ADDR_LO_MASK … #define AMD_PMC_BASE_ADDR_HI_MASK … /* SMU Response Codes */ #define AMD_PMC_RESULT_OK … #define AMD_PMC_RESULT_CMD_REJECT_BUSY … #define AMD_PMC_RESULT_CMD_REJECT_PREREQ … #define AMD_PMC_RESULT_CMD_UNKNOWN … #define AMD_PMC_RESULT_FAILED … /* FCH SSC Registers */ #define FCH_S0I3_ENTRY_TIME_L_OFFSET … #define FCH_S0I3_ENTRY_TIME_H_OFFSET … #define FCH_S0I3_EXIT_TIME_L_OFFSET … #define FCH_S0I3_EXIT_TIME_H_OFFSET … #define FCH_SSC_MAPPING_SIZE … #define FCH_BASE_PHY_ADDR_LOW … #define FCH_BASE_PHY_ADDR_HIGH … /* SMU Message Definations */ #define SMU_MSG_GETSMUVERSION … #define SMU_MSG_LOG_GETDRAM_ADDR_HI … #define SMU_MSG_LOG_GETDRAM_ADDR_LO … #define SMU_MSG_LOG_START … #define SMU_MSG_LOG_RESET … #define SMU_MSG_LOG_DUMP_DATA … #define SMU_MSG_GET_SUP_CONSTRAINTS … #define PMC_MSG_DELAY_MIN_US … #define RESPONSE_REGISTER_LOOP_MAX … #define DELAY_MIN_US … #define DELAY_MAX_US … #define FIFO_SIZE … enum amd_pmc_def { … }; enum s2d_arg { … }; struct amd_pmc_stb_v2_data { … }; struct amd_pmc_bit_map { … }; static const struct amd_pmc_bit_map soc15_ip_blk[] = …; static bool enable_stb; module_param(enable_stb, bool, 0644); MODULE_PARM_DESC(…) …; static bool disable_workarounds; module_param(disable_workarounds, bool, 0644); MODULE_PARM_DESC(…) …; static bool dump_custom_stb; module_param(dump_custom_stb, bool, 0644); MODULE_PARM_DESC(…) …; static struct amd_pmc_dev pmc; static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf); static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data); static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) { … } static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) { … } struct smu_metrics { … } __packed; static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp) { … } static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, loff_t *pos) { … } static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp) { … } static const struct file_operations amd_pmc_stb_debugfs_fops = …; /* Enhanced STB Firmware Reporting Mechanism */ static int amd_pmc_stb_handle_efr(struct file *filp) { … } static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp) { … } static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size, loff_t *pos) { … } static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp) { … } static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = …; static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev) { … } static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) { … } static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) { … } static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) { … } static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) { … } static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, char *buf) { … } static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RO(smu_fw_version); static DEVICE_ATTR_RO(smu_program); static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) { … } static struct attribute *pmc_attrs[] = …; static struct attribute_group pmc_attr_group = …; static const struct attribute_group *pmc_groups[] = …; static int smu_fw_info_show(struct seq_file *s, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); static int s0ix_stats_show(struct seq_file *s, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, struct seq_file *s) { … } static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) { … } static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev) { … } static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) { … } static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) { … } static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) { … } static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) { … } static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) { … } static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) { … } static void amd_pmc_s2idle_prepare(void) { … } static void amd_pmc_s2idle_check(void) { … } static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) { … } static void amd_pmc_s2idle_restore(void) { … } static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = …; static int amd_pmc_suspend_handler(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL); static const struct pci_device_id pmc_pci_ids[] = …; static int amd_pmc_s2d_init(struct amd_pmc_dev *dev) { … } static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data) { … } static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf) { … } static int amd_pmc_probe(struct platform_device *pdev) { … } static void amd_pmc_remove(struct platform_device *pdev) { … } static const struct acpi_device_id amd_pmc_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); static struct platform_driver amd_pmc_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …;
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