/* SPDX-License-Identifier: GPL-2.0 */ /* * Intel Core SoC Power Management Controller Header File * * Copyright (c) 2016, Intel Corporation. * All Rights Reserved. * * Authors: Rajneesh Bhardwaj <[email protected]> * Vishwanath Somayaji <[email protected]> */ #ifndef PMC_CORE_H #define PMC_CORE_H #include <linux/acpi.h> #include <linux/bits.h> #include <linux/platform_device.h> struct telem_endpoint; #define SLP_S0_RES_COUNTER_MASK … #define PMC_BASE_ADDR_DEFAULT … #define MAX_NUM_PMC … #define S0IX_BLK_SIZE … /* Sunrise Point Power Management Controller PCI Device ID */ #define SPT_PMC_PCI_DEVICE_ID … #define SPT_PMC_BASE_ADDR_OFFSET … #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET … #define SPT_PMC_PM_CFG_OFFSET … #define SPT_PMC_PM_STS_OFFSET … #define SPT_PMC_MTPMC_OFFSET … #define SPT_PMC_MFPMC_OFFSET … #define SPT_PMC_LTR_IGNORE_OFFSET … #define SPT_PMC_VRIC1_OFFSET … #define SPT_PMC_MPHY_CORE_STS_0 … #define SPT_PMC_MPHY_CORE_STS_1 … #define SPT_PMC_MPHY_COM_STS_0 … #define SPT_PMC_MMIO_REG_LEN … #define SPT_PMC_SLP_S0_RES_COUNTER_STEP … #define PMC_BASE_ADDR_MASK … #define MTPMC_MASK … #define PPFEAR_MAX_NUM_ENTRIES … #define SPT_PPFEAR_NUM_ENTRIES … #define SPT_PMC_READ_DISABLE_BIT … #define SPT_PMC_MSG_FULL_STS_BIT … #define NUM_RETRIES … #define SPT_NUM_IP_IGN_ALLOWED … #define SPT_PMC_LTR_CUR_PLT … #define SPT_PMC_LTR_CUR_ASLT … #define SPT_PMC_LTR_SPA … #define SPT_PMC_LTR_SPB … #define SPT_PMC_LTR_SATA … #define SPT_PMC_LTR_GBE … #define SPT_PMC_LTR_XHCI … #define SPT_PMC_LTR_RESERVED … #define SPT_PMC_LTR_ME … #define SPT_PMC_LTR_EVA … #define SPT_PMC_LTR_SPC … #define SPT_PMC_LTR_AZ … #define SPT_PMC_LTR_LPSS … #define SPT_PMC_LTR_CAM … #define SPT_PMC_LTR_SPD … #define SPT_PMC_LTR_SPE … #define SPT_PMC_LTR_ESPI … #define SPT_PMC_LTR_SCC … #define SPT_PMC_LTR_ISH … /* Sunrise Point: PGD PFET Enable Ack Status Registers */ enum ppfear_regs { … }; #define SPT_PMC_BIT_PMC … #define SPT_PMC_BIT_OPI … #define SPT_PMC_BIT_SPI … #define SPT_PMC_BIT_XHCI … #define SPT_PMC_BIT_SPA … #define SPT_PMC_BIT_SPB … #define SPT_PMC_BIT_SPC … #define SPT_PMC_BIT_GBE … #define SPT_PMC_BIT_SATA … #define SPT_PMC_BIT_HDA_PGD0 … #define SPT_PMC_BIT_HDA_PGD1 … #define SPT_PMC_BIT_HDA_PGD2 … #define SPT_PMC_BIT_HDA_PGD3 … #define SPT_PMC_BIT_RSVD_0B … #define SPT_PMC_BIT_LPSS … #define SPT_PMC_BIT_LPC … #define SPT_PMC_BIT_SMB … #define SPT_PMC_BIT_ISH … #define SPT_PMC_BIT_P2SB … #define SPT_PMC_BIT_DFX … #define SPT_PMC_BIT_SCC … #define SPT_PMC_BIT_RSVD_0C … #define SPT_PMC_BIT_FUSE … #define SPT_PMC_BIT_CAMREA … #define SPT_PMC_BIT_RSVD_0D … #define SPT_PMC_BIT_USB3_OTG … #define SPT_PMC_BIT_EXI … #define SPT_PMC_BIT_CSE … #define SPT_PMC_BIT_CSME_KVM … #define SPT_PMC_BIT_CSME_PMT … #define SPT_PMC_BIT_CSME_CLINK … #define SPT_PMC_BIT_CSME_PTIO … #define SPT_PMC_BIT_CSME_USBR … #define SPT_PMC_BIT_CSME_SUSRAM … #define SPT_PMC_BIT_CSME_SMT … #define SPT_PMC_BIT_RSVD_1A … #define SPT_PMC_BIT_CSME_SMS2 … #define SPT_PMC_BIT_CSME_SMS1 … #define SPT_PMC_BIT_CSME_RTC … #define SPT_PMC_BIT_CSME_PSF … #define SPT_PMC_BIT_MPHY_LANE0 … #define SPT_PMC_BIT_MPHY_LANE1 … #define SPT_PMC_BIT_MPHY_LANE2 … #define SPT_PMC_BIT_MPHY_LANE3 … #define SPT_PMC_BIT_MPHY_LANE4 … #define SPT_PMC_BIT_MPHY_LANE5 … #define SPT_PMC_BIT_MPHY_LANE6 … #define SPT_PMC_BIT_MPHY_LANE7 … #define SPT_PMC_BIT_MPHY_LANE8 … #define SPT_PMC_BIT_MPHY_LANE9 … #define SPT_PMC_BIT_MPHY_LANE10 … #define SPT_PMC_BIT_MPHY_LANE11 … #define SPT_PMC_BIT_MPHY_LANE12 … #define SPT_PMC_BIT_MPHY_LANE13 … #define SPT_PMC_BIT_MPHY_LANE14 … #define SPT_PMC_BIT_MPHY_LANE15 … #define SPT_PMC_BIT_MPHY_CMN_LANE0 … #define SPT_PMC_BIT_MPHY_CMN_LANE1 … #define SPT_PMC_BIT_MPHY_CMN_LANE2 … #define SPT_PMC_BIT_MPHY_CMN_LANE3 … #define SPT_PMC_VRIC1_SLPS0LVEN … #define SPT_PMC_VRIC1_XTALSDQDIS … /* Cannonlake Power Management Controller register offsets */ #define CNP_PMC_SLPS0_DBG_OFFSET … #define CNP_PMC_PM_CFG_OFFSET … #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET … #define CNP_PMC_LTR_IGNORE_OFFSET … /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ #define CNP_PMC_HOST_PPFEAR0A … #define CNP_PMC_LATCH_SLPS0_EVENTS … #define CNP_PMC_MMIO_REG_LEN … #define CNP_PPFEAR_NUM_ENTRIES … #define CNP_PMC_READ_DISABLE_BIT … #define CNP_NUM_IP_IGN_ALLOWED … #define CNP_PMC_LTR_CUR_PLT … #define CNP_PMC_LTR_CUR_ASLT … #define CNP_PMC_LTR_SPA … #define CNP_PMC_LTR_SPB … #define CNP_PMC_LTR_SATA … #define CNP_PMC_LTR_GBE … #define CNP_PMC_LTR_XHCI … #define CNP_PMC_LTR_RESERVED … #define CNP_PMC_LTR_ME … #define CNP_PMC_LTR_EVA … #define CNP_PMC_LTR_SPC … #define CNP_PMC_LTR_AZ … #define CNP_PMC_LTR_LPSS … #define CNP_PMC_LTR_CAM … #define CNP_PMC_LTR_SPD … #define CNP_PMC_LTR_SPE … #define CNP_PMC_LTR_ESPI … #define CNP_PMC_LTR_SCC … #define CNP_PMC_LTR_ISH … #define CNP_PMC_LTR_CNV … #define CNP_PMC_LTR_EMMC … #define CNP_PMC_LTR_UFSX2 … #define LTR_DECODED_VAL … #define LTR_DECODED_SCALE … #define LTR_REQ_SNOOP … #define LTR_REQ_NONSNOOP … #define ICL_PPFEAR_NUM_ENTRIES … #define ICL_NUM_IP_IGN_ALLOWED … #define ICL_PMC_LTR_WIGIG … #define ICL_PMC_SLP_S0_RES_COUNTER_STEP … #define LPM_MAX_NUM_MODES … #define LPM_DEFAULT_PRI … #define GET_X2_COUNTER(v) … #define LPM_STS_LATCH_MODE … #define TGL_PMC_SLP_S0_RES_COUNTER_STEP … #define TGL_PMC_LTR_THC0 … #define TGL_PMC_LTR_THC1 … #define TGL_NUM_IP_IGN_ALLOWED … #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 … #define ADL_PMC_LTR_SPF … #define ADL_NUM_IP_IGN_ALLOWED … #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET … /* * Tigerlake Power Management Controller register offsets */ #define TGL_LPM_STS_LATCH_EN_OFFSET … #define TGL_LPM_EN_OFFSET … #define TGL_LPM_RESIDENCY_OFFSET … /* Tigerlake Low Power Mode debug registers */ #define TGL_LPM_STATUS_OFFSET … #define TGL_LPM_LIVE_STATUS_OFFSET … #define TGL_LPM_PRI_OFFSET … #define TGL_LPM_NUM_MAPS … /* Tigerlake PSON residency register */ #define TGL_PSON_RESIDENCY_OFFSET … #define TGL_PSON_RES_COUNTER_STEP … /* Extended Test Mode Register 3 (CNL and later) */ #define ETR3_OFFSET … #define ETR3_CF9GR … #define ETR3_CF9LOCK … /* Extended Test Mode Register LPM bits (TGL and later */ #define ETR3_CLEAR_LPM_EVENTS … /* Alder Lake Power Management Controller register offsets */ #define ADL_LPM_EN_OFFSET … #define ADL_LPM_RESIDENCY_OFFSET … #define ADL_LPM_NUM_MODES … #define ADL_LPM_NUM_MAPS … /* Alder Lake Low Power Mode debug registers */ #define ADL_LPM_STATUS_OFFSET … #define ADL_LPM_PRI_OFFSET … #define ADL_LPM_STATUS_LATCH_EN_OFFSET … #define ADL_LPM_LIVE_STATUS_OFFSET … /* Meteor Lake Power Management Controller register offsets */ #define MTL_LPM_EN_OFFSET … #define MTL_LPM_RESIDENCY_OFFSET … /* Meteor Lake Low Power Mode debug registers */ #define MTL_LPM_PRI_OFFSET … #define MTL_LPM_STATUS_LATCH_EN_OFFSET … #define MTL_LPM_STATUS_OFFSET … #define MTL_LPM_LIVE_STATUS_OFFSET … #define MTL_PMC_LTR_IOE_PMC … #define MTL_PMC_LTR_ESE … #define MTL_PMC_LTR_RESERVED … #define MTL_IOE_PMC_MMIO_REG_LEN … #define MTL_SOCM_NUM_IP_IGN_ALLOWED … #define MTL_SOC_PMC_MMIO_REG_LEN … #define MTL_PMC_LTR_SPG … #define ARL_SOCS_PMC_LTR_RESERVED … #define ARL_SOCS_NUM_IP_IGN_ALLOWED … #define ARL_PMC_LTR_DMI3 … #define ARL_PCH_PMC_MMIO_REG_LEN … /* Meteor Lake PGD PFET Enable Ack Status */ #define MTL_SOCM_PPFEAR_NUM_ENTRIES … #define MTL_IOE_PPFEAR_NUM_ENTRIES … #define ARL_SOCS_PPFEAR_NUM_ENTRIES … /* Die C6 from PUNIT telemetry */ #define MTL_PMT_DMU_DIE_C6_OFFSET … #define MTL_PMT_DMU_GUID … #define ARL_PMT_DMU_GUID … #define LNL_PMC_MMIO_REG_LEN … #define LNL_PMC_LTR_OSSE … #define LNL_NUM_IP_IGN_ALLOWED … #define LNL_PPFEAR_NUM_ENTRIES … #define LNL_S0IX_BLOCKER_OFFSET … extern const char *pmc_lpm_modes[]; struct pmc_bit_map { … }; /** * struct pmc_reg_map - Structure used to define parameter unique to a PCH family * @pfear_sts: Maps name of IP block to PPFEAR* bit * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit * @pll_sts: Maps name of PLL to corresponding bit status * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets * @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit * @regmap_length: Length of memory to map from PWRMBASE address to access * @ppfear0_offset: PWRMBASE offset to read PPFEAR* * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from * PPFEAR * @pm_cfg_offset: PWRMBASE offset to PM_CFG register * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* * @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter * * Each PCH has unique set of register offsets and bit indexes. This structure * captures them to have a common implementation. */ struct pmc_reg_map { … }; /** * struct pmc_info - Structure to keep pmc info * @devid: device id of the pmc device * @map: pointer to a pmc_reg_map struct that contains platform * specific attributes */ struct pmc_info { … }; /** * struct pmc - pmc private info structure * @base_addr: contains pmc base address * @regbase: pointer to io-remapped memory location * @map: pointer to pmc_reg_map struct that contains platform * specific attributes * @lpm_req_regs: List of substate requirements * * pmc contains info about one power management controller device. */ struct pmc { … }; /** * struct pmc_dev - pmc device structure * @devs: pointer to an array of pmc pointers * @pdev: pointer to platform_device struct * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM * @crystal_freq: crystal frequency from cpuid * @dbgfs_dir: path to debugfs interface * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers * used to read MPHY PG and PLL status are available * @mutex_lock: mutex to complete one transcation * @pkgc_res_cnt: Array of PKGC residency counters * @num_of_pkgc: Number of PKGC * @s0ix_counter: S0ix residency (step adjusted) * @num_lpm_modes: Count of enabled modes * @lpm_en_modes: Array of enabled modes from lowest to highest priority * @suspend: Function to perform platform specific suspend * @resume: Function to perform platform specific resume * * pmc_dev contains info about power management controller device. */ struct pmc_dev { … }; enum pmc_index { … }; extern const struct pmc_bit_map msr_map[]; extern const struct pmc_bit_map spt_pll_map[]; extern const struct pmc_bit_map spt_mphy_map[]; extern const struct pmc_bit_map spt_pfear_map[]; extern const struct pmc_bit_map *ext_spt_pfear_map[]; extern const struct pmc_bit_map spt_ltr_show_map[]; extern const struct pmc_reg_map spt_reg_map; extern const struct pmc_bit_map cnp_pfear_map[]; extern const struct pmc_bit_map *ext_cnp_pfear_map[]; extern const struct pmc_bit_map cnp_slps0_dbg0_map[]; extern const struct pmc_bit_map cnp_slps0_dbg1_map[]; extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; extern const struct pmc_bit_map cnp_ltr_show_map[]; extern const struct pmc_reg_map cnp_reg_map; extern const struct pmc_bit_map icl_pfear_map[]; extern const struct pmc_bit_map *ext_icl_pfear_map[]; extern const struct pmc_reg_map icl_reg_map; extern const struct pmc_bit_map tgl_pfear_map[]; extern const struct pmc_bit_map *ext_tgl_pfear_map[]; extern const struct pmc_bit_map tgl_clocksource_status_map[]; extern const struct pmc_bit_map tgl_power_gating_status_map[]; extern const struct pmc_bit_map tgl_d3_status_map[]; extern const struct pmc_bit_map tgl_vnn_req_status_map[]; extern const struct pmc_bit_map tgl_vnn_misc_status_map[]; extern const struct pmc_bit_map tgl_signal_status_map[]; extern const struct pmc_bit_map *tgl_lpm_maps[]; extern const struct pmc_reg_map tgl_reg_map; extern const struct pmc_reg_map tgl_h_reg_map; extern const struct pmc_bit_map adl_pfear_map[]; extern const struct pmc_bit_map *ext_adl_pfear_map[]; extern const struct pmc_bit_map adl_ltr_show_map[]; extern const struct pmc_bit_map adl_clocksource_status_map[]; extern const struct pmc_bit_map adl_power_gating_status_0_map[]; extern const struct pmc_bit_map adl_power_gating_status_1_map[]; extern const struct pmc_bit_map adl_power_gating_status_2_map[]; extern const struct pmc_bit_map adl_d3_status_0_map[]; extern const struct pmc_bit_map adl_d3_status_1_map[]; extern const struct pmc_bit_map adl_d3_status_2_map[]; extern const struct pmc_bit_map adl_d3_status_3_map[]; extern const struct pmc_bit_map adl_vnn_req_status_0_map[]; extern const struct pmc_bit_map adl_vnn_req_status_1_map[]; extern const struct pmc_bit_map adl_vnn_req_status_2_map[]; extern const struct pmc_bit_map adl_vnn_req_status_3_map[]; extern const struct pmc_bit_map adl_vnn_misc_status_map[]; extern const struct pmc_bit_map *adl_lpm_maps[]; extern const struct pmc_reg_map adl_reg_map; extern const struct pmc_bit_map mtl_socm_pfear_map[]; extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[]; extern const struct pmc_bit_map mtl_socm_ltr_show_map[]; extern const struct pmc_bit_map mtl_socm_clocksource_status_map[]; extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[]; extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[]; extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[]; extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; extern const struct pmc_bit_map mtl_socm_d3_status_2_map[]; extern const struct pmc_bit_map mtl_socm_d3_status_3_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[]; extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; extern const struct pmc_bit_map mtl_socm_signal_status_map[]; extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; extern const struct pmc_reg_map mtl_socm_reg_map; extern const struct pmc_bit_map mtl_ioep_pfear_map[]; extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[]; extern const struct pmc_bit_map mtl_ioep_ltr_show_map[]; extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[]; extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[]; extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[]; extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[]; extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[]; extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[]; extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[]; extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[]; extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[]; extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[]; extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[]; extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[]; extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; extern const struct pmc_reg_map mtl_ioep_reg_map; extern const struct pmc_bit_map mtl_ioem_pfear_map[]; extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[]; extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[]; extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[]; extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; extern const struct pmc_reg_map mtl_ioem_reg_map; extern const struct pmc_reg_map lnl_socm_reg_map; /* LNL */ extern const struct pmc_bit_map lnl_ltr_show_map[]; extern const struct pmc_bit_map lnl_clocksource_status_map[]; extern const struct pmc_bit_map lnl_power_gating_status_0_map[]; extern const struct pmc_bit_map lnl_power_gating_status_1_map[]; extern const struct pmc_bit_map lnl_power_gating_status_2_map[]; extern const struct pmc_bit_map lnl_d3_status_0_map[]; extern const struct pmc_bit_map lnl_d3_status_1_map[]; extern const struct pmc_bit_map lnl_d3_status_2_map[]; extern const struct pmc_bit_map lnl_d3_status_3_map[]; extern const struct pmc_bit_map lnl_vnn_req_status_0_map[]; extern const struct pmc_bit_map lnl_vnn_req_status_1_map[]; extern const struct pmc_bit_map lnl_vnn_req_status_2_map[]; extern const struct pmc_bit_map lnl_vnn_req_status_3_map[]; extern const struct pmc_bit_map lnl_vnn_misc_status_map[]; extern const struct pmc_bit_map *lnl_lpm_maps[]; extern const struct pmc_bit_map *lnl_blk_maps[]; extern const struct pmc_bit_map lnl_pfear_map[]; extern const struct pmc_bit_map *ext_lnl_pfear_map[]; extern const struct pmc_bit_map lnl_signal_status_map[]; /* ARL */ extern const struct pmc_bit_map arl_socs_ltr_show_map[]; extern const struct pmc_bit_map arl_socs_clocksource_status_map[]; extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[]; extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[]; extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[]; extern const struct pmc_bit_map arl_socs_d3_status_2_map[]; extern const struct pmc_bit_map arl_socs_d3_status_3_map[]; extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[]; extern const struct pmc_bit_map *arl_socs_lpm_maps[]; extern const struct pmc_bit_map arl_socs_pfear_map[]; extern const struct pmc_bit_map *ext_arl_socs_pfear_map[]; extern const struct pmc_reg_map arl_socs_reg_map; extern const struct pmc_bit_map arl_pchs_ltr_show_map[]; extern const struct pmc_bit_map arl_pchs_clocksource_status_map[]; extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[]; extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[]; extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[]; extern const struct pmc_bit_map arl_pchs_d3_status_0_map[]; extern const struct pmc_bit_map arl_pchs_d3_status_1_map[]; extern const struct pmc_bit_map arl_pchs_d3_status_2_map[]; extern const struct pmc_bit_map arl_pchs_d3_status_3_map[]; extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[]; extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[]; extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[]; extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[]; extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[]; extern const struct pmc_bit_map arl_pchs_signal_status_map[]; extern const struct pmc_bit_map *arl_pchs_lpm_maps[]; extern const struct pmc_reg_map arl_pchs_reg_map; extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev); int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore); int pmc_core_resume_common(struct pmc_dev *pmcdev); int get_primary_reg_base(struct pmc *pmc); extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); extern void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid); extern void pmc_core_set_device_d3(unsigned int device); extern int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func); int spt_core_init(struct pmc_dev *pmcdev); int cnp_core_init(struct pmc_dev *pmcdev); int icl_core_init(struct pmc_dev *pmcdev); int tgl_core_init(struct pmc_dev *pmcdev); int tgl_l_core_init(struct pmc_dev *pmcdev); int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp); int adl_core_init(struct pmc_dev *pmcdev); int mtl_core_init(struct pmc_dev *pmcdev); int arl_core_init(struct pmc_dev *pmcdev); int lnl_core_init(struct pmc_dev *pmcdev); void cnl_suspend(struct pmc_dev *pmcdev); int cnl_resume(struct pmc_dev *pmcdev); #define pmc_for_each_mode(i, mode, pmcdev) … #define DEFINE_PMC_CORE_ATTR_WRITE(__name) … #endif /* PMC_CORE_H */
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