/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Daire McNamara,<[email protected]> * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ #define CLK_CPU … #define CLK_AXI … #define CLK_AHB … #define CLK_ENVM … #define CLK_MAC0 … #define CLK_MAC1 … #define CLK_MMC … #define CLK_TIMER … #define CLK_MMUART0 … #define CLK_MMUART1 … #define CLK_MMUART2 … #define CLK_MMUART3 … #define CLK_MMUART4 … #define CLK_SPI0 … #define CLK_SPI1 … #define CLK_I2C0 … #define CLK_I2C1 … #define CLK_CAN0 … #define CLK_CAN1 … #define CLK_USB … #define CLK_RESERVED … #define CLK_RTC … #define CLK_QSPI … #define CLK_GPIO0 … #define CLK_GPIO1 … #define CLK_GPIO2 … #define CLK_DDRC … #define CLK_FIC0 … #define CLK_FIC1 … #define CLK_FIC2 … #define CLK_FIC3 … #define CLK_ATHENA … #define CLK_CFM … #define CLK_RTCREF … #define CLK_MSSPLL … #define CLK_MSSPLL0 … #define CLK_MSSPLL1 … #define CLK_MSSPLL2 … #define CLK_MSSPLL3 … /* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */ #define CLK_CCC_PLL0 … #define CLK_CCC_PLL1 … #define CLK_CCC_DLL0 … #define CLK_CCC_DLL1 … #define CLK_CCC_PLL0_OUT0 … #define CLK_CCC_PLL0_OUT1 … #define CLK_CCC_PLL0_OUT2 … #define CLK_CCC_PLL0_OUT3 … #define CLK_CCC_PLL1_OUT0 … #define CLK_CCC_PLL1_OUT1 … #define CLK_CCC_PLL1_OUT2 … #define CLK_CCC_PLL1_OUT3 … #define CLK_CCC_DLL0_OUT0 … #define CLK_CCC_DLL0_OUT1 … #define CLK_CCC_DLL1_OUT0 … #define CLK_CCC_DLL1_OUT1 … #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
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