linux/drivers/clk/microchip/clk-mpfs-ccc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Author: Conor Dooley <[email protected]>
 *
 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
 */
#include <linux/clk-provider.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/microchip,mpfs-clock.h>

/* address offset of control registers */
#define MPFS_CCC_PLL_CR …
#define MPFS_CCC_REF_CR …
#define MPFS_CCC_SSCG_2_CR …
#define MPFS_CCC_POSTDIV01_CR …
#define MPFS_CCC_POSTDIV23_CR …

#define MPFS_CCC_FBDIV_SHIFT …
#define MPFS_CCC_FBDIV_WIDTH …
#define MPFS_CCC_POSTDIV0_SHIFT …
#define MPFS_CCC_POSTDIV1_SHIFT …
#define MPFS_CCC_POSTDIV2_SHIFT …
#define MPFS_CCC_POSTDIV3_SHIFT …
#define MPFS_CCC_POSTDIV_WIDTH …
#define MPFS_CCC_REFCLK_SEL …
#define MPFS_CCC_REFDIV_SHIFT …
#define MPFS_CCC_REFDIV_WIDTH …

#define MPFS_CCC_FIXED_DIV …
#define MPFS_CCC_OUTPUTS_PER_PLL …
#define MPFS_CCC_REFS_PER_PLL …

struct mpfs_ccc_data { … };

struct mpfs_ccc_pll_hw_clock { … };

#define to_mpfs_ccc_clk(_hw) …

/*
 * mpfs_ccc_lock prevents anything else from writing to a fabric ccc
 * while a software locked register is being written.
 */
static DEFINE_SPINLOCK(mpfs_ccc_lock);

static const struct clk_parent_data mpfs_ccc_pll0_refs[] = …;

static const struct clk_parent_data mpfs_ccc_pll1_refs[] = …;

static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
{ … }

static u8 mpfs_ccc_pll_get_parent(struct clk_hw *hw)
{ … }

static const struct clk_ops mpfs_ccc_pll_ops = …;

#define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) …

static struct mpfs_ccc_pll_hw_clock mpfs_ccc_pll_clks[] = …;

struct mpfs_ccc_out_hw_clock { … };

#define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) …

static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll0out_clks[] = …;

static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll1out_clks[] = …;

static struct mpfs_ccc_out_hw_clock *mpfs_ccc_pllout_clks[] = …;

static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_clock *out_hws,
				     unsigned int num_clks, struct mpfs_ccc_data *data,
				     struct mpfs_ccc_pll_hw_clock *parent)
{ … }

#define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) …

static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clock *pll_hws,
				  unsigned int num_clks, struct mpfs_ccc_data *data)
{ … }

static int mpfs_ccc_probe(struct platform_device *pdev)
{ … }

static const struct of_device_id mpfs_ccc_of_match_table[] = …;
MODULE_DEVICE_TABLE(of, mpfs_ccc_of_match_table);

static struct platform_driver mpfs_ccc_driver = …;

static int __init clk_ccc_init(void)
{ … }
core_initcall(clk_ccc_init);

static void __exit clk_ccc_exit(void)
{ … }
module_exit(clk_ccc_exit);

MODULE_DESCRIPTION(…) …;
MODULE_AUTHOR(…) …;