// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Daniel Palmer <[email protected]> */ #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/kernel.h> #include <linux/of_address.h> #include <linux/platform_device.h> /* * This IP is not documented outside of the messy vendor driver. * Below is what we think the registers look like based on looking at * the vendor code and poking at the hardware: * * 0x140 -- LPF low. Seems to store one half of the clock transition * 0x144 / * 0x148 -- LPF high. Seems to store one half of the clock transition * 0x14c / * 0x150 -- vendor code says "toggle lpf enable" * 0x154 -- mu? * 0x15c -- lpf_update_count? * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank? * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to * LPF high. * 0x174 -- Seems to be the PLL lock status bit * 0x180 -- Seems to be the current frequency, this might need to be populated by software? * 0x184 / The vendor driver uses these to set the initial value of LPF low * * Frequency seems to be calculated like this: * (parent clock (432mhz) / register_magic_value) * 16 * 524288 * Only the lower 24 bits of the resulting value will be used. In addition, the * PLL doesn't seem to be able to lock on frequencies lower than 220 MHz, as * divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up. * * Vendor values: * frequency - register value * * 400000000 - 0x0067AE14 * 600000000 - 0x00451EB8, * 800000000 - 0x0033D70A, * 1000000000 - 0x002978d4, */ #define REG_LPF_LOW_L … #define REG_LPF_LOW_H … #define REG_LPF_HIGH_BOTTOM … #define REG_LPF_HIGH_TOP … #define REG_LPF_TOGGLE … #define REG_LPF_MYSTERYTWO … #define REG_LPF_UPDATE_COUNT … #define REG_LPF_MYSTERYONE … #define REG_LPF_TRANSITIONCTRL … #define REG_LPF_LOCK … #define REG_CURRENT … #define LPF_LOCK_TIMEOUT … #define MULTIPLIER_1 … #define MULTIPLIER_2 … #define MULTIPLIER … struct msc313_cpupll { … }; #define to_cpupll(_hw) … static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned int reg) { … } static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsigned int reg, u32 value) { … } static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue) { … } static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long parent_rate) { … } static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long parent_rate) { … } static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long msc313_cpupll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int msc313_cpupll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops msc313_cpupll_ops = …; static const struct of_device_id msc313_cpupll_of_match[] = …; static int msc313_cpupll_probe(struct platform_device *pdev) { … } static struct platform_driver msc313_cpupll_driver = …; builtin_platform_driver(…) …;
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