linux/drivers/clk/pistachio/clk-pll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Google, Inc.
 */

#define pr_fmt(fmt)

#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/printk.h>
#include <linux/slab.h>

#include "clk.h"

#define PLL_STATUS
#define PLL_STATUS_LOCK

#define PLL_CTRL1
#define PLL_CTRL1_REFDIV_SHIFT
#define PLL_CTRL1_REFDIV_MASK
#define PLL_CTRL1_FBDIV_SHIFT
#define PLL_CTRL1_FBDIV_MASK
#define PLL_INT_CTRL1_POSTDIV1_SHIFT
#define PLL_INT_CTRL1_POSTDIV1_MASK
#define PLL_INT_CTRL1_POSTDIV2_SHIFT
#define PLL_INT_CTRL1_POSTDIV2_MASK
#define PLL_INT_CTRL1_PD
#define PLL_INT_CTRL1_DSMPD
#define PLL_INT_CTRL1_FOUTPOSTDIVPD
#define PLL_INT_CTRL1_FOUTVCOPD

#define PLL_CTRL2
#define PLL_FRAC_CTRL2_FRAC_SHIFT
#define PLL_FRAC_CTRL2_FRAC_MASK
#define PLL_FRAC_CTRL2_POSTDIV1_SHIFT
#define PLL_FRAC_CTRL2_POSTDIV1_MASK
#define PLL_FRAC_CTRL2_POSTDIV2_SHIFT
#define PLL_FRAC_CTRL2_POSTDIV2_MASK
#define PLL_INT_CTRL2_BYPASS

#define PLL_CTRL3
#define PLL_FRAC_CTRL3_PD
#define PLL_FRAC_CTRL3_DACPD
#define PLL_FRAC_CTRL3_DSMPD
#define PLL_FRAC_CTRL3_FOUTPOSTDIVPD
#define PLL_FRAC_CTRL3_FOUT4PHASEPD
#define PLL_FRAC_CTRL3_FOUTVCOPD

#define PLL_CTRL4
#define PLL_FRAC_CTRL4_BYPASS

#define MIN_PFD
#define MIN_VCO_LA
#define MAX_VCO_LA
#define MIN_VCO_FRAC_INT
#define MAX_VCO_FRAC_INT
#define MIN_VCO_FRAC_FRAC
#define MAX_VCO_FRAC_FRAC
#define MIN_OUTPUT_LA
#define MAX_OUTPUT_LA
#define MIN_OUTPUT_FRAC
#define MAX_OUTPUT_FRAC

/* Fractional PLL operating modes */
enum pll_mode {};

struct pistachio_clk_pll {};

static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)
{}

static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
{}

static inline void pll_lock(struct pistachio_clk_pll *pll)
{}

static inline u64 do_div_round_closest(u64 dividend, u64 divisor)
{}

static inline struct pistachio_clk_pll *to_pistachio_pll(struct clk_hw *hw)
{}

static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw)
{}

static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode)
{}

static struct pistachio_pll_rate_table *
pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
	       unsigned long fout)
{}

static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
			   unsigned long *parent_rate)
{}

static int pll_gf40lp_frac_enable(struct clk_hw *hw)
{}

static void pll_gf40lp_frac_disable(struct clk_hw *hw)
{}

static int pll_gf40lp_frac_is_enabled(struct clk_hw *hw)
{}

static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate)
{}

static unsigned long pll_gf40lp_frac_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{}

static const struct clk_ops pll_gf40lp_frac_ops =;

static const struct clk_ops pll_gf40lp_frac_fixed_ops =;

static int pll_gf40lp_laint_enable(struct clk_hw *hw)
{}

static void pll_gf40lp_laint_disable(struct clk_hw *hw)
{}

static int pll_gf40lp_laint_is_enabled(struct clk_hw *hw)
{}

static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long parent_rate)
{}

static unsigned long pll_gf40lp_laint_recalc_rate(struct clk_hw *hw,
						  unsigned long parent_rate)
{}

static const struct clk_ops pll_gf40lp_laint_ops =;

static const struct clk_ops pll_gf40lp_laint_fixed_ops =;

static struct clk *pll_register(const char *name, const char *parent_name,
				unsigned long flags, void __iomem *base,
				enum pistachio_pll_type type,
				struct pistachio_pll_rate_table *rates,
				unsigned int nr_rates)
{}

void pistachio_clk_register_pll(struct pistachio_clk_provider *p,
				struct pistachio_pll *pll,
				unsigned int num)
{}