clk-rcg.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>

#include <asm/div64.h>

#include "clk-rcg.h"
#include "common.h"

static u32 ns_to_src(struct src_sel *s, u32 ns)
{ … }

static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
{ … }

static u8 clk_rcg_get_parent(struct clk_hw *hw)
{ … }

static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
{ … }

static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
{ … }

static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
{ … }

static u32 md_to_m(struct mn *mn, u32 md)
{ … }

static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
{ … }

static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
{ … }

static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
{ … }

static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
{ … }

static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
{ … }

static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
{ … }

static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
{ … }

static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
{ … }

static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
{ … }

/*
 * Calculate m/n:d rate
 *
 *          parent_rate     m
 *   rate = ----------- x  ---
 *            pre_div       n
 */
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
{ … }

static unsigned long
clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ … }

static unsigned long
clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ … }

static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
		struct clk_rate_request *req,
		const struct parent_map *parent_map)
{ … }

static int clk_rcg_determine_rate(struct clk_hw *hw,
				  struct clk_rate_request *req)
{ … }

static int clk_dyn_rcg_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{ … }

static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
					 struct clk_rate_request *req)
{ … }

static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
{ … }

static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{ … }

static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate,
				  unsigned long parent_rate)
{ … }

static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

static int clk_rcg_bypass2_determine_rate(struct clk_hw *hw,
				struct clk_rate_request *req)
{ … }

static int clk_rcg_bypass2_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

static int clk_rcg_bypass2_set_rate_and_parent(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate, u8 index)
{ … }

struct frac_entry { … };

static const struct frac_entry pixel_table[] = …;

static int clk_rcg_pixel_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
{ … }

static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

static int clk_rcg_pixel_set_rate_and_parent(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate, u8 index)
{ … }

static int clk_rcg_esc_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
{ … }

static int clk_rcg_esc_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

static int clk_rcg_esc_set_rate_and_parent(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate, u8 index)
{ … }

/*
 * This type of clock has a glitch-free mux that switches between the output of
 * the M/N counter and an always on clock source (XO). When clk_set_rate() is
 * called we need to make sure that we don't switch to the M/N counter if it
 * isn't clocking because the mux will get stuck and the clock will stop
 * outputting a clock. This can happen if the framework isn't aware that this
 * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
 * this we switch the mux in the enable/disable ops and reprogram the M/N
 * counter in the set_rate op. We also make sure to switch away from the M/N
 * counter in set_rate if software thinks the clock is off.
 */
static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

static int clk_rcg_lcc_enable(struct clk_hw *hw)
{ … }

static void clk_rcg_lcc_disable(struct clk_hw *hw)
{ … }

static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
{ … }

static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{ … }

static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate, u8 index)
{ … }

const struct clk_ops clk_rcg_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_rcg_floor_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_rcg_bypass_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_rcg_bypass2_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_rcg_pixel_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_rcg_esc_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_rcg_lcc_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_dyn_rcg_ops = …;
EXPORT_SYMBOL_GPL(…);
linux/drivers/clk/qcom/clk-rcg.c
