linux/drivers/clk/qcom/clk-regmap-mux-div.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2017, Linaro Limited
 * Author: Georgi Djakov <[email protected]>
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/regmap.h>

#include "clk-regmap-mux-div.h"

#define CMD_RCGR …
#define CMD_RCGR_UPDATE …
#define CMD_RCGR_DIRTY_CFG …
#define CMD_RCGR_ROOT_OFF …
#define CFG_RCGR …

#define to_clk_regmap_mux_div(_hw) …

int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
{ … }
EXPORT_SYMBOL_GPL(…);

static void mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
				u32 *div)
{ … }

static inline bool is_better_rate(unsigned long req, unsigned long best,
				  unsigned long new)
{ … }

static int mux_div_determine_rate(struct clk_hw *hw,
				  struct clk_rate_request *req)
{ … }

static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
					 unsigned long prate, u32 src)
{ … }

static u8 mux_div_get_parent(struct clk_hw *hw)
{ … }

static int mux_div_set_parent(struct clk_hw *hw, u8 index)
{ … }

static int mux_div_set_rate(struct clk_hw *hw,
			    unsigned long rate, unsigned long prate)
{ … }

static int mux_div_set_rate_and_parent(struct clk_hw *hw,  unsigned long rate,
				       unsigned long prate, u8 index)
{ … }

static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
{ … }

const struct clk_ops clk_regmap_mux_div_ops = …;
EXPORT_SYMBOL_GPL(…);