// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/kernel.h> #include <linux/export.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/delay.h> #include "clk-alpha-pll.h" #include "common.h" #define PLL_MODE(p) … #define PLL_OUTCTRL … #define PLL_BYPASSNL … #define PLL_RESET_N … #define PLL_OFFLINE_REQ … #define PLL_LOCK_COUNT_SHIFT … #define PLL_LOCK_COUNT_MASK … #define PLL_BIAS_COUNT_SHIFT … #define PLL_BIAS_COUNT_MASK … #define PLL_VOTE_FSM_ENA … #define PLL_FSM_ENA … #define PLL_VOTE_FSM_RESET … #define PLL_UPDATE … #define PLL_UPDATE_BYPASS … #define PLL_FSM_LEGACY_MODE … #define PLL_OFFLINE_ACK … #define ALPHA_PLL_ACK_LATCH … #define PLL_ACTIVE_FLAG … #define PLL_LOCK_DET … #define PLL_L_VAL(p) … #define PLL_CAL_L_VAL(p) … #define PLL_ALPHA_VAL(p) … #define PLL_ALPHA_VAL_U(p) … #define PLL_USER_CTL(p) … #define PLL_POST_DIV_SHIFT … #define PLL_POST_DIV_MASK(p) … #define PLL_ALPHA_EN … #define PLL_ALPHA_MODE … #define PLL_VCO_SHIFT … #define PLL_VCO_MASK … #define PLL_USER_CTL_U(p) … #define PLL_USER_CTL_U1(p) … #define PLL_CONFIG_CTL(p) … #define PLL_CONFIG_CTL_U(p) … #define PLL_CONFIG_CTL_U1(p) … #define PLL_CONFIG_CTL_U2(p) … #define PLL_TEST_CTL(p) … #define PLL_TEST_CTL_U(p) … #define PLL_TEST_CTL_U1(p) … #define PLL_TEST_CTL_U2(p) … #define PLL_STATUS(p) … #define PLL_OPMODE(p) … #define PLL_FRAC(p) … const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = …; EXPORT_SYMBOL_GPL(…); /* * Even though 40 bits are present, use only 32 for ease of calculation. */ #define ALPHA_REG_BITWIDTH … #define ALPHA_REG_16BIT_WIDTH … #define ALPHA_BITWIDTH … #define ALPHA_SHIFT(w) … #define ALPHA_PLL_STATUS_REG_SHIFT … #define PLL_HUAYRA_M_WIDTH … #define PLL_HUAYRA_M_SHIFT … #define PLL_HUAYRA_M_MASK … #define PLL_HUAYRA_N_SHIFT … #define PLL_HUAYRA_N_MASK … #define PLL_HUAYRA_ALPHA_WIDTH … #define PLL_STANDBY … #define PLL_RUN … #define PLL_OUT_MASK … #define PLL_RATE_MARGIN … /* TRION PLL specific settings and offsets */ #define TRION_PLL_CAL_VAL … #define TRION_PCAL_DONE … /* LUCID PLL specific settings and offsets */ #define LUCID_PCAL_DONE … /* LUCID 5LPE PLL specific settings and offsets */ #define LUCID_5LPE_PCAL_DONE … #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH … #define LUCID_5LPE_PLL_LATCH_INPUT … #define LUCID_5LPE_ENABLE_VOTE_RUN … /* LUCID EVO PLL specific settings and offsets */ #define LUCID_EVO_PCAL_NOT_DONE … #define LUCID_EVO_ENABLE_VOTE_RUN … #define LUCID_EVO_PLL_L_VAL_MASK … #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT … #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT … /* ZONDA PLL specific */ #define ZONDA_PLL_OUT_MASK … #define ZONDA_STAY_IN_CFA … #define ZONDA_PLL_FREQ_LOCK_DET … #define pll_alpha_width(p) … #define pll_has_64bit_config(p) … #define to_clk_alpha_pll(_hw) … #define to_clk_alpha_pll_postdiv(_hw) … static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, const char *action) { … } #define wait_for_pll_enable_active(pll) … #define wait_for_pll_enable_lock(pll) … #define wait_for_zonda_pll_freq_lock(pll) … #define wait_for_pll_disable(pll) … #define wait_for_pll_offline(pll) … #define wait_for_pll_update(pll) … #define wait_for_pll_update_ack_set(pll) … #define wait_for_pll_update_ack_clear(pll) … static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, unsigned int val) { … } void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) { … } static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) { … } static int pll_is_enabled(struct clk_hw *hw, u32 mask) { … } static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) { … } static int clk_alpha_pll_is_enabled(struct clk_hw *hw) { … } static int clk_alpha_pll_enable(struct clk_hw *hw) { … } static void clk_alpha_pll_disable(struct clk_hw *hw) { … } static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) { … } static unsigned long alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, u32 alpha_width) { … } static const struct pll_vco * alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) { … } static unsigned long clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) { … } static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, int (*is_enabled)(struct clk_hw *)) { … } static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, int (*is_enabled)(struct clk_hw *)) { … } static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static unsigned long alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) { … } static unsigned long alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u32 *a) { … } static unsigned long alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int trion_pll_is_enabled(struct clk_alpha_pll *pll, struct regmap *regmap) { … } static int clk_trion_pll_is_enabled(struct clk_hw *hw) { … } static int clk_trion_pll_enable(struct clk_hw *hw) { … } static void clk_trion_pll_disable(struct clk_hw *hw) { … } static unsigned long clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } const struct clk_ops clk_alpha_pll_fixed_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_huayra_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_hwfsm_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_fixed_trion_ops = …; EXPORT_SYMBOL_GPL(…); static unsigned long clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_div_table clk_alpha_div_table[] = …; static const struct clk_div_table clk_alpha_2bit_div_table[] = …; static long clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static long clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } const struct clk_ops clk_alpha_pll_postdiv_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_postdiv_ro_ops = …; EXPORT_SYMBOL_GPL(…); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static int alpha_pll_fabia_enable(struct clk_hw *hw) { … } static void alpha_pll_fabia_disable(struct clk_hw *hw) { … } static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } /* * Due to limited number of bits for fractional rate programming, the * rounded up rate could be marginally higher than the requested rate. */ static int alpha_pll_check_rate_margin(struct clk_hw *hw, unsigned long rrate, unsigned long rate) { … } static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } static int alpha_pll_fabia_prepare(struct clk_hw *hw) { … } const struct clk_ops clk_alpha_pll_fabia_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_fixed_fabia_ops = …; EXPORT_SYMBOL_GPL(…); static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); return divider_round_rate(hw, rate, prate, pll->post_div_table, pll->width, CLK_DIVIDER_ROUND_CLOSEST); }; static int clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } const struct clk_ops clk_alpha_pll_postdiv_trion_ops = …; EXPORT_SYMBOL_GPL(…); static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = …; EXPORT_SYMBOL_GPL(…); /** * clk_trion_pll_configure - configure the trion pll * * @pll: clk alpha pll * @regmap: register map * @config: configuration to apply for pll */ void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); /* * The TRION PLL requires a power-on self-calibration which happens when the * PLL comes out of reset. Calibrate in case it is not completed. */ static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) { … } static int alpha_pll_trion_prepare(struct clk_hw *hw) { … } static int alpha_pll_lucid_prepare(struct clk_hw *hw) { … } static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, u32 latch_bit, u32 latch_ack) { … } static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } const struct clk_ops clk_alpha_pll_trion_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_lucid_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = …; EXPORT_SYMBOL_GPL(…); void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } const struct clk_ops clk_alpha_pll_agera_ops = …; EXPORT_SYMBOL_GPL(…); static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) { … } static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) { … } /* * The Lucid 5LPE PLL requires a power-on self-calibration which happens * when the PLL comes out of reset. Calibrate in case it is not completed. */ static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) { … } static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, unsigned long enable_vote_run) { … } static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = …; EXPORT_SYMBOL_GPL(…); void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static int clk_zonda_pll_enable(struct clk_hw *hw) { … } static void clk_zonda_pll_disable(struct clk_hw *hw) { … } static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } const struct clk_ops clk_alpha_pll_zonda_ops = …; EXPORT_SYMBOL_GPL(…); void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) { … } static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) { … } static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) { … } static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) { … } static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) { … } static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) { … } static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) { … } static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_lucid_evo_ops = …; EXPORT_SYMBOL_GPL(…); const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = …; EXPORT_SYMBOL_GPL(…); void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } const struct clk_ops clk_alpha_pll_rivian_evo_ops = …; EXPORT_SYMBOL_GPL(…); void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { … } EXPORT_SYMBOL_GPL(…); static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } const struct clk_ops clk_alpha_pll_stromer_ops = …; EXPORT_SYMBOL_GPL(…); static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { … } const struct clk_ops clk_alpha_pll_stromer_plus_ops = …; EXPORT_SYMBOL_GPL(…);
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