// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. */ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/export.h> #include <linux/jiffies.h> #include <linux/kernel.h> #include <linux/ktime.h> #include <linux/pm_domain.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/reset-controller.h> #include <linux/slab.h> #include "gdsc.h" #define PWR_ON_MASK … #define EN_REST_WAIT_MASK … #define EN_FEW_WAIT_MASK … #define CLK_DIS_WAIT_MASK … #define SW_OVERRIDE_MASK … #define HW_CONTROL_MASK … #define SW_COLLAPSE_MASK … #define GMEM_CLAMP_IO_MASK … #define GMEM_RESET_MASK … /* CFG_GDSCR */ #define GDSC_POWER_UP_COMPLETE … #define GDSC_POWER_DOWN_COMPLETE … #define GDSC_RETAIN_FF_ENABLE … #define CFG_GDSCR_OFFSET … /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ #define EN_REST_WAIT_VAL … #define EN_FEW_WAIT_VAL … #define CLK_DIS_WAIT_VAL … /* Transition delay shifts */ #define EN_REST_WAIT_SHIFT … #define EN_FEW_WAIT_SHIFT … #define CLK_DIS_WAIT_SHIFT … #define RETAIN_MEM … #define RETAIN_PERIPH … #define STATUS_POLL_TIMEOUT_US … #define TIMEOUT_US … #define domain_to_gdsc(domain) … enum gdsc_status { … }; /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) { … } static int gdsc_hwctrl(struct gdsc *sc, bool en) { … } static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) { … } static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) { … } static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status, bool wait) { … } static inline int gdsc_deassert_reset(struct gdsc *sc) { … } static inline int gdsc_assert_reset(struct gdsc *sc) { … } static inline void gdsc_force_mem_on(struct gdsc *sc) { … } static inline void gdsc_clear_mem_on(struct gdsc *sc) { … } static inline void gdsc_deassert_clamp_io(struct gdsc *sc) { … } static inline void gdsc_assert_clamp_io(struct gdsc *sc) { … } static inline void gdsc_assert_reset_aon(struct gdsc *sc) { … } static void gdsc_retain_ff_on(struct gdsc *sc) { … } static int gdsc_enable(struct generic_pm_domain *domain) { … } static int gdsc_disable(struct generic_pm_domain *domain) { … } static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) { … } static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev) { … } static int gdsc_init(struct gdsc *sc) { … } int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *rcdev, struct regmap *regmap) { … } void gdsc_unregister(struct gdsc_desc *desc) { … } /* * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU * running in the CX domain so the CPU doesn't need to know anything about the * GX domain EXCEPT.... * * Hardware constraints dictate that the GX be powered down before the CX. If * the GMU crashes it could leave the GX on. In order to successfully bring back * the device the CPU needs to disable the GX headswitch. There being no sane * way to reach in and touch that register from deep inside the GPU driver we * need to set up the infrastructure to be able to ensure that the GPU can * ensure that the GX is off during this super special case. We do this by * defining a GX gdsc with a dummy enable function and a "default" disable * function. * * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU * driver. During power up, nothing will happen from the CPU (and the GMU will * power up normally but during power down this will ensure that the GX domain * is *really* off - this gives us a semi standard way of doing what we need. */ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) { … } EXPORT_SYMBOL_GPL(…);
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