linux/drivers/mailbox/imx-mailbox.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <[email protected]>
 * Copyright 2022 NXP, Peng Fan <[email protected]>
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/s4.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
#include <linux/slab.h>
#include <linux/workqueue.h>

#include "mailbox.h"

#define IMX_MU_CHANS
/* TX0/RX0/RXDB[0-3] */
#define IMX_MU_SCU_CHANS
/* TX0/RX0 */
#define IMX_MU_S4_CHANS
#define IMX_MU_CHAN_NAME_SIZE

#define IMX_MU_V2_PAR_OFF
#define IMX_MU_V2_TR_MASK
#define IMX_MU_V2_RR_MASK

#define IMX_MU_SECO_TX_TOUT
#define IMX_MU_SECO_RX_TOUT

/* Please not change TX & RX */
enum imx_mu_chan_type {};

enum imx_mu_xcr {};

enum imx_mu_xsr {};

struct imx_sc_rpc_msg_max {};

struct imx_s4_rpc_msg_max {};

struct imx_mu_con_priv {};

struct imx_mu_priv {};

enum imx_mu_type {};

struct imx_mu_dcfg {};

#define IMX_MU_xSR_GIPn(type, x)
#define IMX_MU_xSR_RFn(type, x)
#define IMX_MU_xSR_TEn(type, x)

/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(type, x)
/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(type, x)
/* Transmit Interrupt Enable */
#define IMX_MU_xCR_TIEn(type, x)
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(type, x)
/* MU reset */
#define IMX_MU_xCR_RST(type)
#define IMX_MU_xSR_RST(type)


static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{}

static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
{}

static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
{}

static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
{}

static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
{}

static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
{}

static int imx_mu_generic_tx(struct imx_mu_priv *priv,
			     struct imx_mu_con_priv *cp,
			     void *data)
{}

static int imx_mu_generic_rx(struct imx_mu_priv *priv,
			     struct imx_mu_con_priv *cp)
{}

static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
			       struct imx_mu_con_priv *cp)
{}

static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
{}

static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
{}

static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
			  void *data)
{}

static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
{}

static void imx_mu_txdb_work(struct work_struct *t)
{}

static irqreturn_t imx_mu_isr(int irq, void *p)
{}

static int imx_mu_send_data(struct mbox_chan *chan, void *data)
{}

static int imx_mu_startup(struct mbox_chan *chan)
{}

static void imx_mu_shutdown(struct mbox_chan *chan)
{}

static const struct mbox_chan_ops imx_mu_ops =;

static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
					       const struct of_phandle_args *sp)
{}

static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
				       const struct of_phandle_args *sp)
{}

static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
					   const struct of_phandle_args *sp)
{}

static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
{}

static int imx_mu_init_generic(struct imx_mu_priv *priv)
{}

static int imx_mu_init_specific(struct imx_mu_priv *priv)
{}

static int imx_mu_init_seco(struct imx_mu_priv *priv)
{}

static int imx_mu_probe(struct platform_device *pdev)
{}

static void imx_mu_remove(struct platform_device *pdev)
{}

static const struct imx_mu_dcfg imx_mu_cfg_imx6sx =;

static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp =;

static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp =;

static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 =;

static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 =;

static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu =;

static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco =;

static const struct of_device_id imx_mu_dt_ids[] =;
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);

static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
{}

static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
{}

static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
{}

static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
{}

static const struct dev_pm_ops imx_mu_pm_ops =;

static struct platform_driver imx_mu_driver =;
module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();