// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2016 Broadcom */ /* * Broadcom PDC Mailbox Driver * The PDC provides a ring based programming interface to one or more hardware * offload engines. For example, the PDC driver works with both SPU-M and SPU2 * cryptographic offload hardware. In some chips the PDC is referred to as MDE, * and in others the FA2/FA+ hardware is used with this PDC driver. * * The PDC driver registers with the Linux mailbox framework as a mailbox * controller, once for each PDC instance. Ring 0 for each PDC is registered as * a mailbox channel. The PDC driver uses interrupts to determine when data * transfers to and from an offload engine are complete. The PDC driver uses * threaded IRQs so that response messages are handled outside of interrupt * context. * * The PDC driver allows multiple messages to be pending in the descriptor * rings. The tx_msg_start descriptor index indicates where the last message * starts. The txin_numd value at this index indicates how many descriptor * indexes make up the message. Similar state is kept on the receive side. When * an rx interrupt indicates a response is ready, the PDC driver processes numd * descriptors from the tx and rx ring, thus processing one response at a time. */ #include <linux/errno.h> #include <linux/module.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/debugfs.h> #include <linux/interrupt.h> #include <linux/wait.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/mailbox_controller.h> #include <linux/mailbox/brcm-message.h> #include <linux/scatterlist.h> #include <linux/dma-direction.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/workqueue.h> #define PDC_SUCCESS … #define RING_ENTRY_SIZE … /* # entries in PDC dma ring */ #define PDC_RING_ENTRIES … /* * Minimum number of ring descriptor entries that must be free to tell mailbox * framework that it can submit another request */ #define PDC_RING_SPACE_MIN … #define PDC_RING_SIZE … /* Rings are 8k aligned */ #define RING_ALIGN_ORDER … #define RING_ALIGN … #define RX_BUF_ALIGN_ORDER … #define RX_BUF_ALIGN … /* descriptor bumping macros */ #define XXD(x, max_mask) … #define TXD(x, max_mask) … #define RXD(x, max_mask) … #define NEXTTXD(i, max_mask) … #define PREVTXD(i, max_mask) … #define NEXTRXD(i, max_mask) … #define PREVRXD(i, max_mask) … #define NTXDACTIVE(h, t, max_mask) … #define NRXDACTIVE(h, t, max_mask) … /* Length of BCM header at start of SPU msg, in bytes */ #define BCM_HDR_LEN … /* * PDC driver reserves ringset 0 on each SPU for its own use. The driver does * not currently support use of multiple ringsets on a single PDC engine. */ #define PDC_RINGSET … /* * Interrupt mask and status definitions. Enable interrupts for tx and rx on * ring 0 */ #define PDC_RCVINT_0 … #define PDC_RCVINTEN_0 … #define PDC_INTMASK … #define PDC_LAZY_FRAMECOUNT … #define PDC_LAZY_TIMEOUT … #define PDC_LAZY_INT … #define PDC_INTMASK_OFFSET … #define PDC_INTSTATUS_OFFSET … #define PDC_RCVLAZY0_OFFSET … #define FA_RCVLAZY0_OFFSET … /* * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata * before frame */ #define PDC_SPU2_RESP_HDR_LEN … #define PDC_CKSUM_CTRL … #define PDC_CKSUM_CTRL_OFFSET … #define PDC_SPUM_RESP_HDR_LEN … /* * Sets the following bits for write to transmit control reg: * 11 - PtyChkDisable - parity check is disabled * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory */ #define PDC_TX_CTL … /* Bit in tx control reg to enable tx channel */ #define PDC_TX_ENABLE … /* * Sets the following bits for write to receive control reg: * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf * 9 - SepRxHdrDescEn - place start of new frames only in descriptors * that have StartOfFrame set * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all * remaining bytes in current frame, report error * in rx frame status for current frame * 11 - PtyChkDisable - parity check is disabled * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory */ #define PDC_RX_CTL … /* Bit in rx control reg to enable rx channel */ #define PDC_RX_ENABLE … #define CRYPTO_D64_RS0_CD_MASK … /* descriptor flags */ #define D64_CTRL1_EOT … #define D64_CTRL1_IOC … #define D64_CTRL1_EOF … #define D64_CTRL1_SOF … #define RX_STATUS_OVERFLOW … #define RX_STATUS_LEN … #define PDC_TXREGS_OFFSET … #define PDC_RXREGS_OFFSET … /* Maximum size buffer the DMA engine can handle */ #define PDC_DMA_BUF_MAX … enum pdc_hw { … }; /* dma descriptor */ struct dma64dd { … }; /* dma registers per channel(xmt or rcv) */ struct dma64_regs { … }; /* cpp contortions to concatenate w/arg prescan */ #ifndef PAD #define _PADLINE(line) … #define _XSTR(line) … #define PAD … #endif /* PAD */ /* dma registers. matches hw layout. */ struct dma64 { … }; /* PDC registers */ struct pdc_regs { … }; /* structure for allocating/freeing DMA rings */ struct pdc_ring_alloc { … }; /* * context associated with a receive descriptor. * @rxp_ctx: opaque context associated with frame that starts at each * rx ring index. * @dst_sg: Scatterlist used to form reply frames beginning at a given ring * index. Retained in order to unmap each sg after reply is processed. * @rxin_numd: Number of rx descriptors associated with the message that starts * at a descriptor index. Not set for every index. For example, * if descriptor index i points to a scatterlist with 4 entries, * then the next three descriptor indexes don't have a value set. * @resp_hdr: Virtual address of buffer used to catch DMA rx status * @resp_hdr_daddr: physical address of DMA rx status buffer */ struct pdc_rx_ctx { … }; /* PDC state structure */ struct pdc_state { … }; /* Global variables */ struct pdc_globals { … }; static struct pdc_globals pdcg; /* top level debug FS directory for PDC driver */ static struct dentry *debugfs_dir; static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf, size_t count, loff_t *offp) { … } static const struct file_operations pdc_debugfs_stats = …; /** * pdc_setup_debugfs() - Create the debug FS directories. If the top-level * directory has not yet been created, create it now. Create a stats file in * this directory for a SPU. * @pdcs: PDC state structure */ static void pdc_setup_debugfs(struct pdc_state *pdcs) { … } static void pdc_free_debugfs(void) { … } /** * pdc_build_rxd() - Build DMA descriptor to receive SPU result. * @pdcs: PDC state for SPU that will generate result * @dma_addr: DMA address of buffer that descriptor is being built for * @buf_len: Length of the receive buffer, in bytes * @flags: Flags to be stored in descriptor */ static inline void pdc_build_rxd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len, u32 flags) { … } /** * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to * hardware. * @pdcs: PDC state for the SPU that will process this request * @dma_addr: DMA address of packet to be transmitted * @buf_len: Length of tx buffer, in bytes * @flags: Flags to be stored in descriptor */ static inline void pdc_build_txd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len, u32 flags) { … } /** * pdc_receive_one() - Receive a response message from a given SPU. * @pdcs: PDC state for the SPU to receive from * * When the return code indicates success, the response message is available in * the receive buffers provided prior to submission of the request. * * Return: PDC_SUCCESS if one or more receive descriptors was processed * -EAGAIN indicates that no response message is available * -EIO an error occurred */ static int pdc_receive_one(struct pdc_state *pdcs) { … } /** * pdc_receive() - Process as many responses as are available in the rx ring. * @pdcs: PDC state * * Called within the hard IRQ. * Return: */ static int pdc_receive(struct pdc_state *pdcs) { … } /** * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit * descriptors for a given SPU. The scatterlist buffers contain the data for a * SPU request message. * @pdcs: PDC state for the SPU that will process this request * @sg: Scatterlist whose buffers contain part of the SPU request * * If a scatterlist buffer is larger than PDC_DMA_BUF_MAX, multiple descriptors * are written for that buffer, each <= PDC_DMA_BUF_MAX byte in length. * * Return: PDC_SUCCESS if successful * < 0 otherwise */ static int pdc_tx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg) { … } /** * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx * ring. * @pdcs: PDC state for SPU to process the request * * Sets the index of the last descriptor written in both the rx and tx ring. * * Return: PDC_SUCCESS */ static int pdc_tx_list_final(struct pdc_state *pdcs) { … } /** * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC. * @pdcs: PDC state for SPU handling request * @dst_sg: scatterlist providing rx buffers for response to be returned to * mailbox client * @ctx: Opaque context for this request * * Posts a single receive descriptor to hold the metadata that precedes a * response. For example, with SPU-M, the metadata is a 32-byte DMA header and * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and * rx to indicate the start of a new message. * * Return: PDC_SUCCESS if successful * < 0 if an error (e.g., rx ring is full) */ static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg, void *ctx) { … } /** * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive * descriptors for a given SPU. The caller must have already DMA mapped the * scatterlist. * @pdcs: PDC state for the SPU that will process this request * @sg: Scatterlist whose buffers are added to the receive ring * * If a receive buffer in the scatterlist is larger than PDC_DMA_BUF_MAX, * multiple receive descriptors are written, each with a buffer <= * PDC_DMA_BUF_MAX. * * Return: PDC_SUCCESS if successful * < 0 otherwise (e.g., receive ring is full) */ static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg) { … } /** * pdc_irq_handler() - Interrupt handler called in interrupt context. * @irq: Interrupt number that has fired * @data: device struct for DMA engine that generated the interrupt * * We have to clear the device interrupt status flags here. So cache the * status for later use in the thread function. Other than that, just return * WAKE_THREAD to invoke the thread function. * * Return: IRQ_WAKE_THREAD if interrupt is ours * IRQ_NONE otherwise */ static irqreturn_t pdc_irq_handler(int irq, void *data) { … } /** * pdc_work_cb() - Work callback that runs the deferred processing after * a DMA receive interrupt. Reenables the receive interrupt. * @t: Pointer to the Altera sSGDMA channel structure */ static void pdc_work_cb(struct work_struct *t) { … } /** * pdc_ring_init() - Allocate DMA rings and initialize constant fields of * descriptors in one ringset. * @pdcs: PDC instance state * @ringset: index of ringset being used * * Return: PDC_SUCCESS if ring initialized * < 0 otherwise */ static int pdc_ring_init(struct pdc_state *pdcs, int ringset) { … } static void pdc_ring_free(struct pdc_state *pdcs) { … } /** * pdc_desc_count() - Count the number of DMA descriptors that will be required * for a given scatterlist. Account for the max length of a DMA buffer. * @sg: Scatterlist to be DMA'd * Return: Number of descriptors required */ static u32 pdc_desc_count(struct scatterlist *sg) { … } /** * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors * and the rx ring has room for rx_cnt descriptors. * @pdcs: PDC state * @tx_cnt: The number of descriptors required in the tx ring * @rx_cnt: The number of descriptors required i the rx ring * * Return: true if one of the rings does not have enough space * false if sufficient space is available in both rings */ static bool pdc_rings_full(struct pdc_state *pdcs, int tx_cnt, int rx_cnt) { … } /** * pdc_last_tx_done() - If both the tx and rx rings have at least * PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox * framework can submit another message. * @chan: mailbox channel to check * Return: true if PDC can accept another message on this channel */ static bool pdc_last_tx_done(struct mbox_chan *chan) { … } /** * pdc_send_data() - mailbox send_data function * @chan: The mailbox channel on which the data is sent. The channel * corresponds to a DMA ringset. * @data: The mailbox message to be sent. The message must be a * brcm_message structure. * * This function is registered as the send_data function for the mailbox * controller. From the destination scatterlist in the mailbox message, it * creates a sequence of receive descriptors in the rx ring. From the source * scatterlist, it creates a sequence of transmit descriptors in the tx ring. * After creating the descriptors, it writes the rx ptr and tx ptr registers to * initiate the DMA transfer. * * This function does the DMA map and unmap of the src and dst scatterlists in * the mailbox message. * * Return: 0 if successful * -ENOTSUPP if the mailbox message is a type this driver does not * support * < 0 if an error */ static int pdc_send_data(struct mbox_chan *chan, void *data) { … } static int pdc_startup(struct mbox_chan *chan) { … } static void pdc_shutdown(struct mbox_chan *chan) { … } /** * pdc_hw_init() - Use the given initialization parameters to initialize the * state for one of the PDCs. * @pdcs: state of the PDC */ static void pdc_hw_init(struct pdc_state *pdcs) { … } /** * pdc_hw_disable() - Disable the tx and rx control in the hw. * @pdcs: PDC state structure * */ static void pdc_hw_disable(struct pdc_state *pdcs) { … } /** * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata * header returned with each response message. * @pdcs: PDC state structure * * The metadata is not returned to the mailbox client. So the PDC driver * manages these buffers. * * Return: PDC_SUCCESS * -ENOMEM if pool creation fails */ static int pdc_rx_buf_pool_create(struct pdc_state *pdcs) { … } /** * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and * specify a threaded IRQ handler for deferred handling of interrupts outside of * interrupt context. * @pdcs: PDC state * * Set the interrupt mask for transmit and receive done. * Set the lazy interrupt frame count to generate an interrupt for just one pkt. * * Return: PDC_SUCCESS * <0 if threaded irq request fails */ static int pdc_interrupts_init(struct pdc_state *pdcs) { … } static const struct mbox_chan_ops pdc_mbox_chan_ops = …; /** * pdc_mb_init() - Initialize the mailbox controller. * @pdcs: PDC state * * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel * driver only uses one ringset and thus one mb channel. PDC uses the transmit * complete interrupt to determine when a mailbox message has successfully been * transmitted. * * Return: 0 on success * < 0 if there is an allocation or registration failure */ static int pdc_mb_init(struct pdc_state *pdcs) { … } /* Device tree API */ static const int pdc_hw = …; static const int fa_hw = …; static const struct of_device_id pdc_mbox_of_match[] = …; MODULE_DEVICE_TABLE(of, pdc_mbox_of_match); /** * pdc_dt_read() - Read application-specific data from device tree. * @pdev: Platform device * @pdcs: PDC state * * Reads the number of bytes of receive status that precede each received frame. * Reads whether transmit and received frames should be preceded by an 8-byte * BCM header. * * Return: 0 if successful * -ENODEV if device not available */ static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs) { … } /** * pdc_probe() - Probe function for PDC driver. * @pdev: PDC platform device * * Reserve and map register regions defined in device tree. * Allocate and initialize tx and rx DMA rings. * Initialize a mailbox controller for each PDC. * * Return: 0 if successful * < 0 if an error */ static int pdc_probe(struct platform_device *pdev) { … } static void pdc_remove(struct platform_device *pdev) { … } static struct platform_driver pdc_mbox_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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