// SPDX-License-Identifier: GPL-2.0-only // // Copyright (C) 2020-2021 Samuel Holland <[email protected]> // #include <linux/clk.h> #include <linux/devfreq.h> #include <linux/err.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/property.h> #define MBUS_CR … #define MBUS_CR_GET_DRAM_TYPE(x) … #define MBUS_CR_DRAM_TYPE_DDR2 … #define MBUS_CR_DRAM_TYPE_DDR3 … #define MBUS_CR_DRAM_TYPE_DDR4 … #define MBUS_CR_DRAM_TYPE_LPDDR2 … #define MBUS_CR_DRAM_TYPE_LPDDR3 … #define MBUS_TMR … #define MBUS_TMR_PERIOD(x) … #define MBUS_PMU_CFG … #define MBUS_PMU_CFG_PERIOD(x) … #define MBUS_PMU_CFG_UNIT … #define MBUS_PMU_CFG_UNIT_B … #define MBUS_PMU_CFG_UNIT_KB … #define MBUS_PMU_CFG_UNIT_MB … #define MBUS_PMU_CFG_ENABLE … #define MBUS_PMU_BWCR(n) … #define MBUS_TOTAL_BWCR … #define MBUS_TOTAL_BWCR_H616 … #define MBUS_MDFSCR … #define MBUS_MDFSCR_BUFFER_TIMING … #define MBUS_MDFSCR_PAD_HOLD … #define MBUS_MDFSCR_BYPASS … #define MBUS_MDFSCR_MODE … #define MBUS_MDFSCR_MODE_DFS … #define MBUS_MDFSCR_MODE_CFS … #define MBUS_MDFSCR_START … #define MBUS_MDFSMRMR … #define DRAM_PWRCTL … #define DRAM_PWRCTL_SELFREF_EN … #define DRAM_RFSHTMG … #define DRAM_RFSHTMG_TREFI(x) … #define DRAM_RFSHTMG_TRFC(x) … #define DRAM_VTFCR … #define DRAM_VTFCR_VTF_ENABLE … #define DRAM_ODTMAP … #define DRAM_DX_MAX … #define DRAM_DXnGCR0(n) … #define DRAM_DXnGCR0_DXODT … #define DRAM_DXnGCR0_DXODT_DYNAMIC … #define DRAM_DXnGCR0_DXODT_ENABLED … #define DRAM_DXnGCR0_DXODT_DISABLED … #define DRAM_DXnGCR0_DXEN … struct sun8i_a33_mbus_variant { … }; struct sun8i_a33_mbus { … }; /* * The unit for this value is (MBUS clock cycles / MBUS_TMR_PERIOD). When * MBUS_TMR_PERIOD is programmed to match the MBUS clock frequency in MHz, as * it is during DRAM init and during probe, the resulting unit is microseconds. */ static int pmu_period = …; module_param(pmu_period, int, 0644); MODULE_PARM_DESC(…) …; static u32 sun8i_a33_mbus_get_peak_bw(struct sun8i_a33_mbus *priv) { … } static void sun8i_a33_mbus_restart_pmu_counters(struct sun8i_a33_mbus *priv) { … } static void sun8i_a33_mbus_update_nominal_bw(struct sun8i_a33_mbus *priv, u32 ddr_freq_mhz) { … } static int sun8i_a33_mbus_set_dram_freq(struct sun8i_a33_mbus *priv, unsigned long freq) { … } static int sun8i_a33_mbus_set_dram_target(struct device *dev, unsigned long *freq, u32 flags) { … } static int sun8i_a33_mbus_get_dram_status(struct device *dev, struct devfreq_dev_status *stat) { … } static int sun8i_a33_mbus_hw_init(struct device *dev, struct sun8i_a33_mbus *priv, unsigned long ddr_freq) { … } static int __maybe_unused sun8i_a33_mbus_suspend(struct device *dev) { … } static int __maybe_unused sun8i_a33_mbus_resume(struct device *dev) { … } static int sun8i_a33_mbus_probe(struct platform_device *pdev) { … } static void sun8i_a33_mbus_remove(struct platform_device *pdev) { … } static const struct sun8i_a33_mbus_variant sun50i_a64_mbus = …; static const struct of_device_id sun8i_a33_mbus_of_match[] = …; MODULE_DEVICE_TABLE(of, sun8i_a33_mbus_of_match); static SIMPLE_DEV_PM_OPS(sun8i_a33_mbus_pm_ops, sun8i_a33_mbus_suspend, sun8i_a33_mbus_resume); static struct platform_driver sun8i_a33_mbus_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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