/* SPDX-License-Identifier: GPL-2.0-only */ /* * Definitions for DDR memories based on JEDEC specs * * Copyright (C) 2012 Texas Instruments, Inc. * * Aneesh V <[email protected]> */ #ifndef __JEDEC_DDR_H #define __JEDEC_DDR_H #include <linux/types.h> /* DDR Densities */ #define DDR_DENSITY_64Mb … #define DDR_DENSITY_128Mb … #define DDR_DENSITY_256Mb … #define DDR_DENSITY_512Mb … #define DDR_DENSITY_1Gb … #define DDR_DENSITY_2Gb … #define DDR_DENSITY_4Gb … #define DDR_DENSITY_8Gb … #define DDR_DENSITY_16Gb … #define DDR_DENSITY_32Gb … /* DDR type */ #define DDR_TYPE_DDR2 … #define DDR_TYPE_DDR3 … #define DDR_TYPE_LPDDR2_S4 … #define DDR_TYPE_LPDDR2_S2 … #define DDR_TYPE_LPDDR2_NVM … #define DDR_TYPE_LPDDR3 … /* DDR IO width */ #define DDR_IO_WIDTH_4 … #define DDR_IO_WIDTH_8 … #define DDR_IO_WIDTH_16 … #define DDR_IO_WIDTH_32 … /* Number of Row bits */ #define R9 … #define R10 … #define R11 … #define R12 … #define R13 … #define R14 … #define R15 … #define R16 … /* Number of Column bits */ #define C7 … #define C8 … #define C9 … #define C10 … #define C11 … #define C12 … /* Number of Banks */ #define B1 … #define B2 … #define B4 … #define B8 … /* Refresh rate in nano-seconds */ #define T_REFI_15_6 … #define T_REFI_7_8 … #define T_REFI_3_9 … /* tRFC values */ #define T_RFC_90 … #define T_RFC_110 … #define T_RFC_130 … #define T_RFC_160 … #define T_RFC_210 … #define T_RFC_300 … #define T_RFC_350 … /* Mode register numbers */ #define DDR_MR0 … #define DDR_MR1 … #define DDR_MR2 … #define DDR_MR3 … #define DDR_MR4 … #define DDR_MR5 … #define DDR_MR6 … #define DDR_MR7 … #define DDR_MR8 … #define DDR_MR9 … #define DDR_MR10 … #define DDR_MR11 … #define DDR_MR16 … #define DDR_MR17 … #define DDR_MR18 … /* * LPDDR2 related defines */ /* MR4 register fields */ #define MR4_SDRAM_REF_RATE_SHIFT … #define MR4_SDRAM_REF_RATE_MASK … #define MR4_TUF_SHIFT … #define MR4_TUF_MASK … /* MR4 SDRAM Refresh Rate field values */ #define SDRAM_TEMP_NOMINAL … #define SDRAM_TEMP_RESERVED_4 … #define SDRAM_TEMP_HIGH_DERATE_REFRESH … #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS … #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN … #define NUM_DDR_ADDR_TABLE_ENTRIES … #define NUM_DDR_TIMING_TABLE_ENTRIES … #define LPDDR2_MANID_SAMSUNG … #define LPDDR2_MANID_QIMONDA … #define LPDDR2_MANID_ELPIDA … #define LPDDR2_MANID_ETRON … #define LPDDR2_MANID_NANYA … #define LPDDR2_MANID_HYNIX … #define LPDDR2_MANID_MOSEL … #define LPDDR2_MANID_WINBOND … #define LPDDR2_MANID_ESMT … #define LPDDR2_MANID_SPANSION … #define LPDDR2_MANID_SST … #define LPDDR2_MANID_ZMOS … #define LPDDR2_MANID_INTEL … #define LPDDR2_MANID_NUMONYX … #define LPDDR2_MANID_MICRON … #define LPDDR2_TYPE_S4 … #define LPDDR2_TYPE_S2 … #define LPDDR2_TYPE_NVM … /* Structure for DDR addressing info from the JEDEC spec */ struct lpddr2_addressing { … }; /* * Structure for timings from the LPDDR2 datasheet * All parameters are in pico seconds(ps) unless explicitly indicated * with a suffix like tRAS_max_ns below */ struct lpddr2_timings { … }; /* * Min value for some parameters in terms of number of tCK cycles(nCK) * Please set to zero parameters that are not valid for a given memory * type */ struct lpddr2_min_tck { … }; extern const struct lpddr2_addressing lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES]; extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; /* Structure of MR8 */ lpddr2_basic_config4; /* * Structure for information about LPDDR2 chip. All parameters are * matching raw values of standard mode register bitfields or set to * -ENOENT if info unavailable. */ struct lpddr2_info { … }; const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id); /* * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. * All parameters are in pico seconds(ps) excluding max_freq, min_freq which * are in Hz. */ struct lpddr3_timings { … }; /* * Min value for some parameters in terms of number of tCK cycles(nCK) * Please set to zero parameters that are not valid for a given memory * type */ struct lpddr3_min_tck { … }; #endif /* __JEDEC_DDR_H */
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