/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ #ifndef MEMORY_TEGRA_MC_H #define MEMORY_TEGRA_MC_H #include <linux/bits.h> #include <linux/io.h> #include <linux/types.h> #include <soc/tegra/mc.h> #define MC_INTSTATUS … #define MC_INTMASK … #define MC_ERR_STATUS … #define MC_ERR_ADR … #define MC_GART_ERROR_REQ … #define MC_EMEM_ADR_CFG … #define MC_DECERR_EMEM_OTHERS_STATUS … #define MC_SECURITY_VIOLATION_STATUS … #define MC_EMEM_ARB_CFG … #define MC_EMEM_ARB_OUTSTANDING_REQ … #define MC_EMEM_ARB_TIMING_RCD … #define MC_EMEM_ARB_TIMING_RP … #define MC_EMEM_ARB_TIMING_RC … #define MC_EMEM_ARB_TIMING_RAS … #define MC_EMEM_ARB_TIMING_FAW … #define MC_EMEM_ARB_TIMING_RRD … #define MC_EMEM_ARB_TIMING_RAP2PRE … #define MC_EMEM_ARB_TIMING_WAP2PRE … #define MC_EMEM_ARB_TIMING_R2R … #define MC_EMEM_ARB_TIMING_W2W … #define MC_EMEM_ARB_TIMING_R2W … #define MC_EMEM_ARB_TIMING_W2R … #define MC_EMEM_ARB_MISC2 … #define MC_EMEM_ARB_DA_TURNS … #define MC_EMEM_ARB_DA_COVERS … #define MC_EMEM_ARB_MISC0 … #define MC_EMEM_ARB_MISC1 … #define MC_EMEM_ARB_RING1_THROTTLE … #define MC_EMEM_ARB_OVERRIDE … #define MC_TIMING_CONTROL_DBG … #define MC_TIMING_CONTROL … #define MC_ERR_VPR_STATUS … #define MC_ERR_VPR_ADR … #define MC_ERR_SEC_STATUS … #define MC_ERR_SEC_ADR … #define MC_ERR_MTS_STATUS … #define MC_ERR_MTS_ADR … #define MC_ERR_ROUTE_SANITY_STATUS … #define MC_ERR_ROUTE_SANITY_ADR … #define MC_ERR_GENERALIZED_CARVEOUT_STATUS … #define MC_ERR_GENERALIZED_CARVEOUT_ADR … #define MC_EMEM_ADR_CFG_CHANNEL_ENABLE … #define MC_GLOBAL_INTSTATUS … #define MC_ERR_ADR_HI … #define MC_INT_DECERR_ROUTE_SANITY … #define MC_INT_DECERR_GENERALIZED_CARVEOUT … #define MC_INT_DECERR_MTS … #define MC_INT_SECERR_SEC … #define MC_INT_DECERR_VPR … #define MC_INT_INVALID_APB_ASID_UPDATE … #define MC_INT_INVALID_SMMU_PAGE … #define MC_INT_ARBITRATION_EMEM … #define MC_INT_SECURITY_VIOLATION … #define MC_INT_INVALID_GART_PAGE … #define MC_INT_DECERR_EMEM … #define MC_ERR_STATUS_TYPE_SHIFT … #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE … #define MC_ERR_STATUS_TYPE_MASK … #define MC_ERR_STATUS_READABLE … #define MC_ERR_STATUS_WRITABLE … #define MC_ERR_STATUS_NONSECURE … #define MC_ERR_STATUS_ADR_HI_SHIFT … #define MC_ERR_STATUS_ADR_HI_MASK … #define MC_ERR_STATUS_SECURITY … #define MC_ERR_STATUS_RW … #define MC_EMEM_ADR_CFG_EMEM_NUMDEV … #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) … #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK … #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK … #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE … #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE … #define MC_EMEM_ARB_OVERRIDE_EACK_MASK … #define MC_TIMING_UPDATE … #define MC_BROADCAST_CHANNEL … static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) { … } static inline struct tegra_mc * icc_provider_to_tegra_mc(struct icc_provider *provider) { … } static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, unsigned long offset) { … } static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, u32 value, unsigned long offset) { … } static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) { … } static inline void mc_writel(const struct tegra_mc *mc, u32 value, unsigned long offset) { … } extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common; #ifdef CONFIG_ARCH_TEGRA_2x_SOC extern const struct tegra_mc_soc tegra20_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_3x_SOC extern const struct tegra_mc_soc tegra30_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_114_SOC extern const struct tegra_mc_soc tegra114_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_124_SOC extern const struct tegra_mc_soc tegra124_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_132_SOC extern const struct tegra_mc_soc tegra132_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_210_SOC extern const struct tegra_mc_soc tegra210_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_186_SOC extern const struct tegra_mc_soc tegra186_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_194_SOC extern const struct tegra_mc_soc tegra194_mc_soc; #endif #ifdef CONFIG_ARCH_TEGRA_234_SOC extern const struct tegra_mc_soc tegra234_mc_soc; #endif #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_114_SOC) || \ defined(CONFIG_ARCH_TEGRA_124_SOC) || \ defined(CONFIG_ARCH_TEGRA_132_SOC) || \ defined(CONFIG_ARCH_TEGRA_210_SOC) int tegra30_mc_probe(struct tegra_mc *mc); extern const struct tegra_mc_ops tegra30_mc_ops; #endif #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ defined(CONFIG_ARCH_TEGRA_194_SOC) || \ defined(CONFIG_ARCH_TEGRA_234_SOC) extern const struct tegra_mc_ops tegra186_mc_ops; #endif irqreturn_t tegra30_mc_handle_irq(int irq, void *data); extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; /* * These IDs are for internal use of Tegra ICC drivers. The ID numbers are * chosen such that they don't conflict with the device-tree ICC node IDs. */ #define TEGRA_ICC_MC … #define TEGRA_ICC_EMC … #define TEGRA_ICC_EMEM … #endif /* MEMORY_TEGRA_MC_H */
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