/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. */ #ifndef TEGRA210_EMC_H #define TEGRA210_EMC_H #include <linux/clk.h> #include <linux/clk/tegra.h> #include <linux/io.h> #include <linux/platform_device.h> #define DVFS_FGCG_HIGH_SPEED_THRESHOLD … #define IOBRICK_DCC_THRESHOLD … #define DVFS_FGCG_MID_SPEED_THRESHOLD … #define EMC_STATUS_UPDATE_TIMEOUT … /* register definitions */ #define EMC_INTSTATUS … #define EMC_INTSTATUS_CLKCHANGE_COMPLETE … #define EMC_DBG … #define EMC_DBG_WRITE_MUX_ACTIVE … #define EMC_DBG_WRITE_ACTIVE_ONLY … #define EMC_CFG … #define EMC_CFG_DRAM_CLKSTOP_PD … #define EMC_CFG_DRAM_CLKSTOP_SR … #define EMC_CFG_DRAM_ACPD … #define EMC_CFG_DYN_SELF_REF … #define EMC_PIN … #define EMC_PIN_PIN_CKE … #define EMC_PIN_PIN_CKEB … #define EMC_PIN_PIN_CKE_PER_DEV … #define EMC_TIMING_CONTROL … #define EMC_RC … #define EMC_RFC … #define EMC_RAS … #define EMC_RP … #define EMC_R2W … #define EMC_W2R … #define EMC_R2P … #define EMC_W2P … #define EMC_RD_RCD … #define EMC_WR_RCD … #define EMC_RRD … #define EMC_REXT … #define EMC_WDV … #define EMC_QUSE … #define EMC_QRST … #define EMC_QSAFE … #define EMC_RDV … #define EMC_REFRESH … #define EMC_BURST_REFRESH_NUM … #define EMC_PDEX2WR … #define EMC_PDEX2RD … #define EMC_PCHG2PDEN … #define EMC_ACT2PDEN … #define EMC_AR2PDEN … #define EMC_RW2PDEN … #define EMC_TXSR … #define EMC_TCKE … #define EMC_TFAW … #define EMC_TRPAB … #define EMC_TCLKSTABLE … #define EMC_TCLKSTOP … #define EMC_TREFBW … #define EMC_TPPD … #define EMC_ODT_WRITE … #define EMC_PDEX2MRR … #define EMC_WEXT … #define EMC_RFC_SLR … #define EMC_MRS_WAIT_CNT2 … #define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT … #define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT … #define EMC_MRS_WAIT_CNT … #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT … #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK … #define EMC_MRS … #define EMC_EMRS … #define EMC_EMRS_USE_EMRS_LONG_CNT … #define EMC_REF … #define EMC_REF_REF_CMD … #define EMC_SELF_REF … #define EMC_MRW … #define EMC_MRW_MRW_OP_SHIFT … #define EMC_MRW_MRW_OP_MASK … #define EMC_MRW_MRW_MA_SHIFT … #define EMC_MRW_USE_MRW_EXT_CNT … #define EMC_MRW_MRW_DEV_SELECTN_SHIFT … #define EMC_MRR … #define EMC_MRR_DEV_SEL_SHIFT … #define EMC_MRR_DEV_SEL_MASK … #define EMC_MRR_MA_SHIFT … #define EMC_MRR_MA_MASK … #define EMC_MRR_DATA_SHIFT … #define EMC_MRR_DATA_MASK … #define EMC_FBIO_SPARE … #define EMC_FBIO_CFG5 … #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT … #define EMC_FBIO_CFG5_DRAM_TYPE_MASK … #define EMC_FBIO_CFG5_CMD_TX_DIS … #define EMC_PDEX2CKE … #define EMC_CKE2PDEN … #define EMC_MPC … #define EMC_EMRS2 … #define EMC_EMRS2_USE_EMRS2_LONG_CNT … #define EMC_MRW2 … #define EMC_MRW3 … #define EMC_MRW4 … #define EMC_R2R … #define EMC_EINPUT … #define EMC_EINPUT_DURATION … #define EMC_PUTERM_EXTRA … #define EMC_TCKESR … #define EMC_TPD … #define EMC_AUTO_CAL_CONFIG … #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START … #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL … #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL … #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE … #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START … #define EMC_EMC_STATUS … #define EMC_EMC_STATUS_MRR_DIVLD … #define EMC_EMC_STATUS_TIMING_UPDATE_STALLED … #define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT … #define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK … #define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT … #define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK … #define EMC_CFG_2 … #define EMC_CFG_DIG_DLL … #define EMC_CFG_DIG_DLL_CFG_DLL_EN … #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK … #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC … #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK … #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT … #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK … #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT … #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK … #define EMC_CFG_DIG_DLL_PERIOD … #define EMC_DIG_DLL_STATUS … #define EMC_DIG_DLL_STATUS_DLL_LOCK … #define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED … #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT … #define EMC_DIG_DLL_STATUS_DLL_OUT_MASK … #define EMC_CFG_DIG_DLL_1 … #define EMC_RDV_MASK … #define EMC_WDV_MASK … #define EMC_RDV_EARLY_MASK … #define EMC_RDV_EARLY … #define EMC_AUTO_CAL_CONFIG8 … #define EMC_ZCAL_INTERVAL … #define EMC_ZCAL_WAIT_CNT … #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK … #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT … #define EMC_ZQ_CAL … #define EMC_ZQ_CAL_DEV_SEL_SHIFT … #define EMC_ZQ_CAL_LONG … #define EMC_ZQ_CAL_ZQ_LATCH_CMD … #define EMC_ZQ_CAL_ZQ_CAL_CMD … #define EMC_FDPD_CTRL_DQ … #define EMC_FDPD_CTRL_CMD … #define EMC_PMACRO_CMD_BRICK_CTRL_FDPD … #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD … #define EMC_PMACRO_BRICK_CTRL_RFU1 … #define EMC_PMACRO_BRICK_CTRL_RFU2 … #define EMC_TR_TIMING_0 … #define EMC_TR_CTRL_1 … #define EMC_TR_RDV … #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE … #define EMC_SEL_DPD_CTRL … #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN … #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN … #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN … #define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN … #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN … #define EMC_PRE_REFRESH_REQ_CNT … #define EMC_DYN_SELF_REF_CONTROL … #define EMC_TXSRDLL … #define EMC_CCFIFO_ADDR … #define EMC_CCFIFO_ADDR_STALL_BY_1 … #define EMC_CCFIFO_ADDR_STALL(x) … #define EMC_CCFIFO_ADDR_OFFSET(x) … #define EMC_CCFIFO_DATA … #define EMC_TR_QPOP … #define EMC_TR_RDV_MASK … #define EMC_TR_QSAFE … #define EMC_TR_QRST … #define EMC_ISSUE_QRST … #define EMC_AUTO_CAL_CONFIG2 … #define EMC_AUTO_CAL_CONFIG3 … #define EMC_TR_DVFS … #define EMC_AUTO_CAL_CHANNEL … #define EMC_IBDLY … #define EMC_OBDLY … #define EMC_TXDSRVTTGEN … #define EMC_WE_DURATION … #define EMC_WS_DURATION … #define EMC_WEV … #define EMC_WSV … #define EMC_CFG_3 … #define EMC_MRW6 … #define EMC_MRW7 … #define EMC_MRW8 … #define EMC_MRW9 … #define EMC_MRW10 … #define EMC_MRW11 … #define EMC_MRW12 … #define EMC_MRW13 … #define EMC_MRW14 … #define EMC_MRW15 … #define EMC_CFG_SYNC … #define EMC_FDPD_CTRL_CMD_NO_RAMP … #define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE … #define EMC_WDV_CHK … #define EMC_CFG_PIPE_2 … #define EMC_CFG_PIPE_CLK … #define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON … #define EMC_CFG_PIPE_1 … #define EMC_CFG_PIPE … #define EMC_QPOP … #define EMC_QUSE_WIDTH … #define EMC_PUTERM_WIDTH … #define EMC_AUTO_CAL_CONFIG7 … #define EMC_REFCTRL2 … #define EMC_FBIO_CFG7 … #define EMC_FBIO_CFG7_CH0_ENABLE … #define EMC_FBIO_CFG7_CH1_ENABLE … #define EMC_DATA_BRLSHFT_0 … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1 … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT … #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK … #define EMC_RFCPB … #define EMC_DQS_BRLSHFT_0 … #define EMC_DQS_BRLSHFT_1 … #define EMC_CMD_BRLSHFT_0 … #define EMC_CMD_BRLSHFT_1 … #define EMC_CMD_BRLSHFT_2 … #define EMC_CMD_BRLSHFT_3 … #define EMC_QUSE_BRLSHFT_0 … #define EMC_AUTO_CAL_CONFIG4 … #define EMC_AUTO_CAL_CONFIG5 … #define EMC_QUSE_BRLSHFT_1 … #define EMC_QUSE_BRLSHFT_2 … #define EMC_CCDMW … #define EMC_QUSE_BRLSHFT_3 … #define EMC_AUTO_CAL_CONFIG6 … #define EMC_DLL_CFG_0 … #define EMC_DLL_CFG_1 … #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT … #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK … #define EMC_CONFIG_SAMPLE_DELAY … #define EMC_CFG_UPDATE … #define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT … #define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK … #define EMC_PMACRO_QUSE_DDLL_RANK0_0 … #define EMC_PMACRO_QUSE_DDLL_RANK0_1 … #define EMC_PMACRO_QUSE_DDLL_RANK0_2 … #define EMC_PMACRO_QUSE_DDLL_RANK0_3 … #define EMC_PMACRO_QUSE_DDLL_RANK0_4 … #define EMC_PMACRO_QUSE_DDLL_RANK0_5 … #define EMC_PMACRO_QUSE_DDLL_RANK1_0 … #define EMC_PMACRO_QUSE_DDLL_RANK1_1 … #define EMC_PMACRO_QUSE_DDLL_RANK1_2 … #define EMC_PMACRO_QUSE_DDLL_RANK1_3 … #define EMC_PMACRO_QUSE_DDLL_RANK1_4 … #define EMC_PMACRO_QUSE_DDLL_RANK1_5 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 … #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 … #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 … #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 … #define EMC_PMACRO_TX_PWRD_0 … #define EMC_PMACRO_TX_PWRD_1 … #define EMC_PMACRO_TX_PWRD_2 … #define EMC_PMACRO_TX_PWRD_3 … #define EMC_PMACRO_TX_PWRD_4 … #define EMC_PMACRO_TX_PWRD_5 … #define EMC_PMACRO_TX_SEL_CLK_SRC_0 … #define EMC_PMACRO_TX_SEL_CLK_SRC_1 … #define EMC_PMACRO_TX_SEL_CLK_SRC_3 … #define EMC_PMACRO_TX_SEL_CLK_SRC_2 … #define EMC_PMACRO_TX_SEL_CLK_SRC_4 … #define EMC_PMACRO_TX_SEL_CLK_SRC_5 … #define EMC_PMACRO_DDLL_BYPASS … #define EMC_PMACRO_DDLL_PWRD_0 … #define EMC_PMACRO_DDLL_PWRD_1 … #define EMC_PMACRO_DDLL_PWRD_2 … #define EMC_PMACRO_CMD_CTRL_0 … #define EMC_PMACRO_CMD_CTRL_1 … #define EMC_PMACRO_CMD_CTRL_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 … #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 … #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 … #define EMC_PMACRO_IB_VREF_DQ_0 … #define EMC_PMACRO_IB_VREF_DQ_1 … #define EMC_PMACRO_IB_VREF_DQS_0 … #define EMC_PMACRO_IB_VREF_DQS_1 … #define EMC_PMACRO_DDLL_LONG_CMD_0 … #define EMC_PMACRO_DDLL_LONG_CMD_1 … #define EMC_PMACRO_DDLL_LONG_CMD_2 … #define EMC_PMACRO_DDLL_LONG_CMD_3 … #define EMC_PMACRO_DDLL_LONG_CMD_4 … #define EMC_PMACRO_DDLL_LONG_CMD_5 … #define EMC_PMACRO_DDLL_SHORT_CMD_0 … #define EMC_PMACRO_DDLL_SHORT_CMD_1 … #define EMC_PMACRO_DDLL_SHORT_CMD_2 … #define EMC_PMACRO_CFG_PM_GLOBAL_0 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 … #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 … #define EMC_PMACRO_VTTGEN_CTRL_0 … #define EMC_PMACRO_VTTGEN_CTRL_1 … #define EMC_PMACRO_BG_BIAS_CTRL_0 … #define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD … #define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD … #define EMC_PMACRO_PAD_CFG_CTRL … #define EMC_PMACRO_ZCTRL … #define EMC_PMACRO_CMD_PAD_RX_CTRL … #define EMC_PMACRO_DATA_PAD_RX_CTRL … #define EMC_PMACRO_CMD_RX_TERM_MODE … #define EMC_PMACRO_DATA_RX_TERM_MODE … #define EMC_PMACRO_CMD_PAD_TX_CTRL … #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC … #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC … #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC … #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC … #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON … #define EMC_PMACRO_DATA_PAD_TX_CTRL … #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF … #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC … #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF … #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC … #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC … #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC … #define EMC_PMACRO_COMMON_PAD_TX_CTRL … #define EMC_PMACRO_AUTOCAL_CFG_COMMON … #define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS … #define EMC_PMACRO_VTTGEN_CTRL_2 … #define EMC_PMACRO_IB_RXRT … #define EMC_PMACRO_TRAINING_CTRL_0 … #define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR … #define EMC_PMACRO_TRAINING_CTRL_1 … #define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR … #define EMC_TRAINING_CTRL … #define EMC_TRAINING_QUSE_CORS_CTRL … #define EMC_TRAINING_QUSE_FINE_CTRL … #define EMC_TRAINING_QUSE_CTRL_MISC … #define EMC_TRAINING_WRITE_FINE_CTRL … #define EMC_TRAINING_WRITE_CTRL_MISC … #define EMC_TRAINING_WRITE_VREF_CTRL … #define EMC_TRAINING_READ_FINE_CTRL … #define EMC_TRAINING_READ_CTRL_MISC … #define EMC_TRAINING_READ_VREF_CTRL … #define EMC_TRAINING_CA_FINE_CTRL … #define EMC_TRAINING_CA_CTRL_MISC … #define EMC_TRAINING_CA_CTRL_MISC1 … #define EMC_TRAINING_CA_VREF_CTRL … #define EMC_TRAINING_SETTLE … #define EMC_TRAINING_MPC … #define EMC_TRAINING_VREF_SETTLE … #define EMC_TRAINING_QUSE_VREF_CTRL … #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 … #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 … #define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS … #define EMC_COPY_TABLE_PARAM_TRIM_REGS … enum burst_regs_list { … }; enum trim_regs_list { … }; enum burst_mc_regs_list { … }; enum { … }; enum { … }; enum { … }; enum { … }; #define VREF_REGS_PER_CHANNEL_SIZE … #define DRAM_TIMINGS_NUM … #define BURST_REGS_PER_CHANNEL_SIZE … #define TRIM_REGS_PER_CHANNEL_SIZE … #define PTFV_ARRAY_SIZE … #define SAVE_RESTORE_MOD_REGS_SIZE … #define TRAINING_MOD_REGS_SIZE … #define BURST_UP_DOWN_REGS_SIZE … #define BURST_MC_REGS_SIZE … #define TRIM_REGS_SIZE … #define BURST_REGS_SIZE … struct tegra210_emc_per_channel_regs { … }; struct tegra210_emc_table_register_offsets { … }; struct tegra210_emc_timing { … }; enum tegra210_emc_refresh { … }; #define DRAM_TYPE_DDR3 … #define DRAM_TYPE_LPDDR4 … #define DRAM_TYPE_LPDDR2 … #define DRAM_TYPE_DDR2 … struct tegra210_emc { … }; struct tegra210_emc_sequence { … }; static inline void emc_writel(struct tegra210_emc *emc, u32 value, unsigned int offset) { … } static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) { … } static inline void emc_channel_writel(struct tegra210_emc *emc, unsigned int channel, u32 value, unsigned int offset) { … } static inline u32 emc_channel_readl(struct tegra210_emc *emc, unsigned int channel, unsigned int offset) { … } static inline void ccfifo_writel(struct tegra210_emc *emc, u32 value, unsigned int offset, u32 delay) { … } static inline u32 div_o3(u32 a, u32 b) { … } /* from tegra210-emc-r21021.c */ extern const struct tegra210_emc_sequence tegra210_emc_r21021; int tegra210_emc_set_refresh(struct tegra210_emc *emc, enum tegra210_emc_refresh refresh); u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip, unsigned int address); void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc); void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set); void tegra210_emc_timing_update(struct tegra210_emc *emc); u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next); struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc, unsigned long rate); void tegra210_emc_adjust_timing(struct tegra210_emc *emc, struct tegra210_emc_timing *timing); int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel, unsigned int offset, u32 bit_mask, bool state); unsigned long tegra210_emc_actual_osc_clocks(u32 in); u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset); void tegra210_emc_dll_disable(struct tegra210_emc *emc); void tegra210_emc_dll_enable(struct tegra210_emc *emc); u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc); u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk, bool flip_backward); u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk, bool flip_backward); void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing); void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc); #endif
Codebase Browser
linux