/* SPDX-License-Identifier: GPL-2.0-only */ /* * Defines for the EMIF driver * * Copyright (C) 2012 Texas Instruments, Inc. * * Benoit Cousson ([email protected]) */ #ifndef __EMIF_H #define __EMIF_H /* * Maximum number of different frequencies supported by EMIF driver * Determines the number of entries in the pointer array for register * cache */ #define EMIF_MAX_NUM_FREQUENCIES … /* State of the core voltage */ #define DDR_VOLTAGE_STABLE … #define DDR_VOLTAGE_RAMPING … /* Defines for timing De-rating */ #define EMIF_NORMAL_TIMINGS … #define EMIF_DERATED_TIMINGS … /* Length of the forced read idle period in terms of cycles */ #define EMIF_READ_IDLE_LEN_VAL … /* * forced read idle interval to be used when voltage * is changed as part of DVFS/DPS - 1ms */ #define READ_IDLE_INTERVAL_DVFS … /* * Forced read idle interval to be used when voltage is stable * 50us - or maximum value will do */ #define READ_IDLE_INTERVAL_NORMAL … /* DLL calibration interval when voltage is NOT stable - 1us */ #define DLL_CALIB_INTERVAL_DVFS … #define DLL_CALIB_ACK_WAIT_VAL … /* Interval between ZQCS commands - hw team recommended value */ #define EMIF_ZQCS_INTERVAL_US … /* Enable ZQ Calibration on exiting Self-refresh */ #define ZQ_SFEXITEN_ENABLE … /* * ZQ Calibration simultaneously on both chip-selects: * Needs one calibration resistor per CS */ #define ZQ_DUALCALEN_DISABLE … #define ZQ_DUALCALEN_ENABLE … #define T_ZQCS_DEFAULT_NS … #define T_ZQCL_DEFAULT_NS … #define T_ZQINIT_DEFAULT_NS … /* DPD_EN */ #define DPD_DISABLE … #define DPD_ENABLE … /* * Default values for the low-power entry to be used if not provided by user. * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512 * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz */ #define EMIF_LP_MODE_TIMEOUT_PERFORMANCE … #define EMIF_LP_MODE_TIMEOUT_POWER … #define EMIF_LP_MODE_FREQ_THRESHOLD … /* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */ #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY … #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY … #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY … #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY … /* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */ #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY … #define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS … /* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */ #define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS … #define EMIF_T_CSTA … #define EMIF_T_PDLL_UL … /* External PHY control registers magic values */ #define EMIF_EXT_PHY_CTRL_1_VAL … #define EMIF_EXT_PHY_CTRL_5_VAL … #define EMIF_EXT_PHY_CTRL_6_VAL … #define EMIF_EXT_PHY_CTRL_7_VAL … #define EMIF_EXT_PHY_CTRL_8_VAL … #define EMIF_EXT_PHY_CTRL_9_VAL … #define EMIF_EXT_PHY_CTRL_10_VAL … #define EMIF_EXT_PHY_CTRL_11_VAL … #define EMIF_EXT_PHY_CTRL_12_VAL … #define EMIF_EXT_PHY_CTRL_13_VAL … #define EMIF_EXT_PHY_CTRL_14_VAL … #define EMIF_EXT_PHY_CTRL_15_VAL … #define EMIF_EXT_PHY_CTRL_16_VAL … #define EMIF_EXT_PHY_CTRL_17_VAL … #define EMIF_EXT_PHY_CTRL_18_VAL … #define EMIF_EXT_PHY_CTRL_19_VAL … #define EMIF_EXT_PHY_CTRL_20_VAL … #define EMIF_EXT_PHY_CTRL_21_VAL … #define EMIF_EXT_PHY_CTRL_22_VAL … #define EMIF_EXT_PHY_CTRL_23_VAL … #define EMIF_EXT_PHY_CTRL_24_VAL … #define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS … /* Registers offset */ #define EMIF_MODULE_ID_AND_REVISION … #define EMIF_STATUS … #define EMIF_SDRAM_CONFIG … #define EMIF_SDRAM_CONFIG_2 … #define EMIF_SDRAM_REFRESH_CONTROL … #define EMIF_SDRAM_REFRESH_CTRL_SHDW … #define EMIF_SDRAM_TIMING_1 … #define EMIF_SDRAM_TIMING_1_SHDW … #define EMIF_SDRAM_TIMING_2 … #define EMIF_SDRAM_TIMING_2_SHDW … #define EMIF_SDRAM_TIMING_3 … #define EMIF_SDRAM_TIMING_3_SHDW … #define EMIF_LPDDR2_NVM_TIMING … #define EMIF_LPDDR2_NVM_TIMING_SHDW … #define EMIF_POWER_MANAGEMENT_CONTROL … #define EMIF_POWER_MANAGEMENT_CTRL_SHDW … #define EMIF_LPDDR2_MODE_REG_DATA … #define EMIF_LPDDR2_MODE_REG_CONFIG … #define EMIF_OCP_CONFIG … #define EMIF_OCP_CONFIG_VALUE_1 … #define EMIF_OCP_CONFIG_VALUE_2 … #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL … #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT … #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT … #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 … #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 … #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 … #define EMIF_PERFORMANCE_COUNTER_1 … #define EMIF_PERFORMANCE_COUNTER_2 … #define EMIF_PERFORMANCE_COUNTER_CONFIG … #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT … #define EMIF_PERFORMANCE_COUNTER_TIME … #define EMIF_MISC_REG … #define EMIF_DLL_CALIB_CTRL … #define EMIF_DLL_CALIB_CTRL_SHDW … #define EMIF_END_OF_INTERRUPT … #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS … #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS … #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS … #define EMIF_LL_OCP_INTERRUPT_STATUS … #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET … #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET … #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR … #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR … #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG … #define EMIF_TEMPERATURE_ALERT_CONFIG … #define EMIF_OCP_ERROR_LOG … #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW … #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL … #define EMIF_READ_WRITE_LEVELING_CONTROL … #define EMIF_DDR_PHY_CTRL_1 … #define EMIF_DDR_PHY_CTRL_1_SHDW … #define EMIF_DDR_PHY_CTRL_2 … #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING … #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING … #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING … #define EMIF_READ_WRITE_EXECUTION_THRESHOLD … #define EMIF_COS_CONFIG … #define EMIF_PHY_STATUS_1 … #define EMIF_PHY_STATUS_2 … #define EMIF_PHY_STATUS_3 … #define EMIF_PHY_STATUS_4 … #define EMIF_PHY_STATUS_5 … #define EMIF_PHY_STATUS_6 … #define EMIF_PHY_STATUS_7 … #define EMIF_PHY_STATUS_8 … #define EMIF_PHY_STATUS_9 … #define EMIF_PHY_STATUS_10 … #define EMIF_PHY_STATUS_11 … #define EMIF_PHY_STATUS_12 … #define EMIF_PHY_STATUS_13 … #define EMIF_PHY_STATUS_14 … #define EMIF_PHY_STATUS_15 … #define EMIF_PHY_STATUS_16 … #define EMIF_PHY_STATUS_17 … #define EMIF_PHY_STATUS_18 … #define EMIF_PHY_STATUS_19 … #define EMIF_PHY_STATUS_20 … #define EMIF_PHY_STATUS_21 … #define EMIF_EXT_PHY_CTRL_1 … #define EMIF_EXT_PHY_CTRL_1_SHDW … #define EMIF_EXT_PHY_CTRL_2 … #define EMIF_EXT_PHY_CTRL_2_SHDW … #define EMIF_EXT_PHY_CTRL_3 … #define EMIF_EXT_PHY_CTRL_3_SHDW … #define EMIF_EXT_PHY_CTRL_4 … #define EMIF_EXT_PHY_CTRL_4_SHDW … #define EMIF_EXT_PHY_CTRL_5 … #define EMIF_EXT_PHY_CTRL_5_SHDW … #define EMIF_EXT_PHY_CTRL_6 … #define EMIF_EXT_PHY_CTRL_6_SHDW … #define EMIF_EXT_PHY_CTRL_7 … #define EMIF_EXT_PHY_CTRL_7_SHDW … #define EMIF_EXT_PHY_CTRL_8 … #define EMIF_EXT_PHY_CTRL_8_SHDW … #define EMIF_EXT_PHY_CTRL_9 … #define EMIF_EXT_PHY_CTRL_9_SHDW … #define EMIF_EXT_PHY_CTRL_10 … #define EMIF_EXT_PHY_CTRL_10_SHDW … #define EMIF_EXT_PHY_CTRL_11 … #define EMIF_EXT_PHY_CTRL_11_SHDW … #define EMIF_EXT_PHY_CTRL_12 … #define EMIF_EXT_PHY_CTRL_12_SHDW … #define EMIF_EXT_PHY_CTRL_13 … #define EMIF_EXT_PHY_CTRL_13_SHDW … #define EMIF_EXT_PHY_CTRL_14 … #define EMIF_EXT_PHY_CTRL_14_SHDW … #define EMIF_EXT_PHY_CTRL_15 … #define EMIF_EXT_PHY_CTRL_15_SHDW … #define EMIF_EXT_PHY_CTRL_16 … #define EMIF_EXT_PHY_CTRL_16_SHDW … #define EMIF_EXT_PHY_CTRL_17 … #define EMIF_EXT_PHY_CTRL_17_SHDW … #define EMIF_EXT_PHY_CTRL_18 … #define EMIF_EXT_PHY_CTRL_18_SHDW … #define EMIF_EXT_PHY_CTRL_19 … #define EMIF_EXT_PHY_CTRL_19_SHDW … #define EMIF_EXT_PHY_CTRL_20 … #define EMIF_EXT_PHY_CTRL_20_SHDW … #define EMIF_EXT_PHY_CTRL_21 … #define EMIF_EXT_PHY_CTRL_21_SHDW … #define EMIF_EXT_PHY_CTRL_22 … #define EMIF_EXT_PHY_CTRL_22_SHDW … #define EMIF_EXT_PHY_CTRL_23 … #define EMIF_EXT_PHY_CTRL_23_SHDW … #define EMIF_EXT_PHY_CTRL_24 … #define EMIF_EXT_PHY_CTRL_24_SHDW … #define EMIF_EXT_PHY_CTRL_25 … #define EMIF_EXT_PHY_CTRL_25_SHDW … #define EMIF_EXT_PHY_CTRL_26 … #define EMIF_EXT_PHY_CTRL_26_SHDW … #define EMIF_EXT_PHY_CTRL_27 … #define EMIF_EXT_PHY_CTRL_27_SHDW … #define EMIF_EXT_PHY_CTRL_28 … #define EMIF_EXT_PHY_CTRL_28_SHDW … #define EMIF_EXT_PHY_CTRL_29 … #define EMIF_EXT_PHY_CTRL_29_SHDW … #define EMIF_EXT_PHY_CTRL_30 … #define EMIF_EXT_PHY_CTRL_30_SHDW … /* Registers shifts and masks */ /* EMIF_MODULE_ID_AND_REVISION */ #define SCHEME_SHIFT … #define SCHEME_MASK … #define MODULE_ID_SHIFT … #define MODULE_ID_MASK … #define RTL_VERSION_SHIFT … #define RTL_VERSION_MASK … #define MAJOR_REVISION_SHIFT … #define MAJOR_REVISION_MASK … #define MINOR_REVISION_SHIFT … #define MINOR_REVISION_MASK … /* STATUS */ #define BE_SHIFT … #define BE_MASK … #define DUAL_CLK_MODE_SHIFT … #define DUAL_CLK_MODE_MASK … #define FAST_INIT_SHIFT … #define FAST_INIT_MASK … #define RDLVLGATETO_SHIFT … #define RDLVLGATETO_MASK … #define RDLVLTO_SHIFT … #define RDLVLTO_MASK … #define WRLVLTO_SHIFT … #define WRLVLTO_MASK … #define PHY_DLL_READY_SHIFT … #define PHY_DLL_READY_MASK … /* SDRAM_CONFIG */ #define SDRAM_TYPE_SHIFT … #define SDRAM_TYPE_MASK … #define IBANK_POS_SHIFT … #define IBANK_POS_MASK … #define DDR_TERM_SHIFT … #define DDR_TERM_MASK … #define DDR2_DDQS_SHIFT … #define DDR2_DDQS_MASK … #define DYN_ODT_SHIFT … #define DYN_ODT_MASK … #define DDR_DISABLE_DLL_SHIFT … #define DDR_DISABLE_DLL_MASK … #define SDRAM_DRIVE_SHIFT … #define SDRAM_DRIVE_MASK … #define CWL_SHIFT … #define CWL_MASK … #define NARROW_MODE_SHIFT … #define NARROW_MODE_MASK … #define CL_SHIFT … #define CL_MASK … #define ROWSIZE_SHIFT … #define ROWSIZE_MASK … #define IBANK_SHIFT … #define IBANK_MASK … #define EBANK_SHIFT … #define EBANK_MASK … #define PAGESIZE_SHIFT … #define PAGESIZE_MASK … /* SDRAM_CONFIG_2 */ #define CS1NVMEN_SHIFT … #define CS1NVMEN_MASK … #define EBANK_POS_SHIFT … #define EBANK_POS_MASK … #define RDBNUM_SHIFT … #define RDBNUM_MASK … #define RDBSIZE_SHIFT … #define RDBSIZE_MASK … /* SDRAM_REFRESH_CONTROL */ #define INITREF_DIS_SHIFT … #define INITREF_DIS_MASK … #define SRT_SHIFT … #define SRT_MASK … #define ASR_SHIFT … #define ASR_MASK … #define PASR_SHIFT … #define PASR_MASK … #define REFRESH_RATE_SHIFT … #define REFRESH_RATE_MASK … /* SDRAM_TIMING_1 */ #define T_RTW_SHIFT … #define T_RTW_MASK … #define T_RP_SHIFT … #define T_RP_MASK … #define T_RCD_SHIFT … #define T_RCD_MASK … #define T_WR_SHIFT … #define T_WR_MASK … #define T_RAS_SHIFT … #define T_RAS_MASK … #define T_RC_SHIFT … #define T_RC_MASK … #define T_RRD_SHIFT … #define T_RRD_MASK … #define T_WTR_SHIFT … #define T_WTR_MASK … /* SDRAM_TIMING_2 */ #define T_XP_SHIFT … #define T_XP_MASK … #define T_ODT_SHIFT … #define T_ODT_MASK … #define T_XSNR_SHIFT … #define T_XSNR_MASK … #define T_XSRD_SHIFT … #define T_XSRD_MASK … #define T_RTP_SHIFT … #define T_RTP_MASK … #define T_CKE_SHIFT … #define T_CKE_MASK … /* SDRAM_TIMING_3 */ #define T_PDLL_UL_SHIFT … #define T_PDLL_UL_MASK … #define T_CSTA_SHIFT … #define T_CSTA_MASK … #define T_CKESR_SHIFT … #define T_CKESR_MASK … #define ZQ_ZQCS_SHIFT … #define ZQ_ZQCS_MASK … #define T_TDQSCKMAX_SHIFT … #define T_TDQSCKMAX_MASK … #define T_RFC_SHIFT … #define T_RFC_MASK … #define T_RAS_MAX_SHIFT … #define T_RAS_MAX_MASK … /* POWER_MANAGEMENT_CONTROL */ #define PD_TIM_SHIFT … #define PD_TIM_MASK … #define DPD_EN_SHIFT … #define DPD_EN_MASK … #define LP_MODE_SHIFT … #define LP_MODE_MASK … #define SR_TIM_SHIFT … #define SR_TIM_MASK … #define CS_TIM_SHIFT … #define CS_TIM_MASK … /* LPDDR2_MODE_REG_DATA */ #define VALUE_0_SHIFT … #define VALUE_0_MASK … /* LPDDR2_MODE_REG_CONFIG */ #define CS_SHIFT … #define CS_MASK … #define REFRESH_EN_SHIFT … #define REFRESH_EN_MASK … #define ADDRESS_SHIFT … #define ADDRESS_MASK … /* OCP_CONFIG */ #define SYS_THRESH_MAX_SHIFT … #define SYS_THRESH_MAX_MASK … #define MPU_THRESH_MAX_SHIFT … #define MPU_THRESH_MAX_MASK … #define LL_THRESH_MAX_SHIFT … #define LL_THRESH_MAX_MASK … /* PERFORMANCE_COUNTER_1 */ #define COUNTER1_SHIFT … #define COUNTER1_MASK … /* PERFORMANCE_COUNTER_2 */ #define COUNTER2_SHIFT … #define COUNTER2_MASK … /* PERFORMANCE_COUNTER_CONFIG */ #define CNTR2_MCONNID_EN_SHIFT … #define CNTR2_MCONNID_EN_MASK … #define CNTR2_REGION_EN_SHIFT … #define CNTR2_REGION_EN_MASK … #define CNTR2_CFG_SHIFT … #define CNTR2_CFG_MASK … #define CNTR1_MCONNID_EN_SHIFT … #define CNTR1_MCONNID_EN_MASK … #define CNTR1_REGION_EN_SHIFT … #define CNTR1_REGION_EN_MASK … #define CNTR1_CFG_SHIFT … #define CNTR1_CFG_MASK … /* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */ #define MCONNID2_SHIFT … #define MCONNID2_MASK … #define REGION_SEL2_SHIFT … #define REGION_SEL2_MASK … #define MCONNID1_SHIFT … #define MCONNID1_MASK … #define REGION_SEL1_SHIFT … #define REGION_SEL1_MASK … /* PERFORMANCE_COUNTER_TIME */ #define TOTAL_TIME_SHIFT … #define TOTAL_TIME_MASK … /* DLL_CALIB_CTRL */ #define ACK_WAIT_SHIFT … #define ACK_WAIT_MASK … #define DLL_CALIB_INTERVAL_SHIFT … #define DLL_CALIB_INTERVAL_MASK … /* END_OF_INTERRUPT */ #define EOI_SHIFT … #define EOI_MASK … /* SYSTEM_OCP_INTERRUPT_RAW_STATUS */ #define DNV_SYS_SHIFT … #define DNV_SYS_MASK … #define TA_SYS_SHIFT … #define TA_SYS_MASK … #define ERR_SYS_SHIFT … #define ERR_SYS_MASK … /* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */ #define DNV_LL_SHIFT … #define DNV_LL_MASK … #define TA_LL_SHIFT … #define TA_LL_MASK … #define ERR_LL_SHIFT … #define ERR_LL_MASK … /* SYSTEM_OCP_INTERRUPT_ENABLE_SET */ #define EN_DNV_SYS_SHIFT … #define EN_DNV_SYS_MASK … #define EN_TA_SYS_SHIFT … #define EN_TA_SYS_MASK … #define EN_ERR_SYS_SHIFT … #define EN_ERR_SYS_MASK … /* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */ #define EN_DNV_LL_SHIFT … #define EN_DNV_LL_MASK … #define EN_TA_LL_SHIFT … #define EN_TA_LL_MASK … #define EN_ERR_LL_SHIFT … #define EN_ERR_LL_MASK … /* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */ #define ZQ_CS1EN_SHIFT … #define ZQ_CS1EN_MASK … #define ZQ_CS0EN_SHIFT … #define ZQ_CS0EN_MASK … #define ZQ_DUALCALEN_SHIFT … #define ZQ_DUALCALEN_MASK … #define ZQ_SFEXITEN_SHIFT … #define ZQ_SFEXITEN_MASK … #define ZQ_ZQINIT_MULT_SHIFT … #define ZQ_ZQINIT_MULT_MASK … #define ZQ_ZQCL_MULT_SHIFT … #define ZQ_ZQCL_MULT_MASK … #define ZQ_REFINTERVAL_SHIFT … #define ZQ_REFINTERVAL_MASK … /* TEMPERATURE_ALERT_CONFIG */ #define TA_CS1EN_SHIFT … #define TA_CS1EN_MASK … #define TA_CS0EN_SHIFT … #define TA_CS0EN_MASK … #define TA_SFEXITEN_SHIFT … #define TA_SFEXITEN_MASK … #define TA_DEVWDT_SHIFT … #define TA_DEVWDT_MASK … #define TA_DEVCNT_SHIFT … #define TA_DEVCNT_MASK … #define TA_REFINTERVAL_SHIFT … #define TA_REFINTERVAL_MASK … /* OCP_ERROR_LOG */ #define MADDRSPACE_SHIFT … #define MADDRSPACE_MASK … #define MBURSTSEQ_SHIFT … #define MBURSTSEQ_MASK … #define MCMD_SHIFT … #define MCMD_MASK … #define MCONNID_SHIFT … #define MCONNID_MASK … /* READ_WRITE_LEVELING_CONTROL */ #define RDWRLVLFULL_START … /* DDR_PHY_CTRL_1 - EMIF4D */ #define DLL_SLAVE_DLY_CTRL_SHIFT_4D … #define DLL_SLAVE_DLY_CTRL_MASK_4D … #define READ_LATENCY_SHIFT_4D … #define READ_LATENCY_MASK_4D … /* DDR_PHY_CTRL_1 - EMIF4D5 */ #define DLL_HALF_DELAY_SHIFT_4D5 … #define DLL_HALF_DELAY_MASK_4D5 … #define READ_LATENCY_SHIFT_4D5 … #define READ_LATENCY_MASK_4D5 … /* DDR_PHY_CTRL_1_SHDW */ #define DDR_PHY_CTRL_1_SHDW_SHIFT … #define DDR_PHY_CTRL_1_SHDW_MASK … #define READ_LATENCY_SHDW_SHIFT … #define READ_LATENCY_SHDW_MASK … #define EMIF_SRAM_AM33_REG_LAYOUT … #define EMIF_SRAM_AM43_REG_LAYOUT … #ifndef __ASSEMBLY__ /* * Structure containing shadow of important registers in EMIF * The calculation function fills in this structure to be later used for * initialisation and DVFS */ struct emif_regs { … }; struct ti_emif_pm_functions; extern unsigned int ti_emif_sram; extern unsigned int ti_emif_sram_sz; extern struct ti_emif_pm_data ti_emif_pm_sram_data; extern struct emif_regs_amx3 ti_emif_regs_amx3; void ti_emif_save_context(void); void ti_emif_restore_context(void); void ti_emif_run_hw_leveling(void); void ti_emif_enter_sr(void); void ti_emif_exit_sr(void); void ti_emif_abort_sr(void); #endif /* __ASSEMBLY__ */ #endif /* __EMIF_H */
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