linux/drivers/iio/accel/adxl372.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * ADXL372 3-Axis Digital Accelerometer core driver
 *
 * Copyright 2018 Analog Devices Inc.
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include "adxl372.h"

/* ADXL372 registers definition */
#define ADXL372_DEVID
#define ADXL372_DEVID_MST
#define ADXL372_PARTID
#define ADXL372_STATUS_1
#define ADXL372_STATUS_2
#define ADXL372_FIFO_ENTRIES_2
#define ADXL372_FIFO_ENTRIES_1
#define ADXL372_X_DATA_H
#define ADXL372_X_DATA_L
#define ADXL372_Y_DATA_H
#define ADXL372_Y_DATA_L
#define ADXL372_Z_DATA_H
#define ADXL372_Z_DATA_L
#define ADXL372_X_MAXPEAK_H
#define ADXL372_X_MAXPEAK_L
#define ADXL372_Y_MAXPEAK_H
#define ADXL372_Y_MAXPEAK_L
#define ADXL372_Z_MAXPEAK_H
#define ADXL372_Z_MAXPEAK_L
#define ADXL372_OFFSET_X
#define ADXL372_OFFSET_Y
#define ADXL372_OFFSET_Z
#define ADXL372_X_THRESH_ACT_H
#define ADXL372_X_THRESH_ACT_L
#define ADXL372_Y_THRESH_ACT_H
#define ADXL372_Y_THRESH_ACT_L
#define ADXL372_Z_THRESH_ACT_H
#define ADXL372_Z_THRESH_ACT_L
#define ADXL372_TIME_ACT
#define ADXL372_X_THRESH_INACT_H
#define ADXL372_X_THRESH_INACT_L
#define ADXL372_Y_THRESH_INACT_H
#define ADXL372_Y_THRESH_INACT_L
#define ADXL372_Z_THRESH_INACT_H
#define ADXL372_Z_THRESH_INACT_L
#define ADXL372_TIME_INACT_H
#define ADXL372_TIME_INACT_L
#define ADXL372_X_THRESH_ACT2_H
#define ADXL372_X_THRESH_ACT2_L
#define ADXL372_Y_THRESH_ACT2_H
#define ADXL372_Y_THRESH_ACT2_L
#define ADXL372_Z_THRESH_ACT2_H
#define ADXL372_Z_THRESH_ACT2_L
#define ADXL372_HPF
#define ADXL372_FIFO_SAMPLES
#define ADXL372_FIFO_CTL
#define ADXL372_INT1_MAP
#define ADXL372_INT2_MAP
#define ADXL372_TIMING
#define ADXL372_MEASURE
#define ADXL372_POWER_CTL
#define ADXL372_SELF_TEST
#define ADXL372_RESET
#define ADXL372_FIFO_DATA

#define ADXL372_DEVID_VAL
#define ADXL372_PARTID_VAL
#define ADXL372_RESET_CODE

/* ADXL372_POWER_CTL */
#define ADXL372_POWER_CTL_MODE_MSK
#define ADXL372_POWER_CTL_MODE(x)

/* ADXL372_MEASURE */
#define ADXL372_MEASURE_LINKLOOP_MSK
#define ADXL372_MEASURE_LINKLOOP_MODE(x)
#define ADXL372_MEASURE_BANDWIDTH_MSK
#define ADXL372_MEASURE_BANDWIDTH_MODE(x)

/* ADXL372_TIMING */
#define ADXL372_TIMING_ODR_MSK
#define ADXL372_TIMING_ODR_MODE(x)

/* ADXL372_FIFO_CTL */
#define ADXL372_FIFO_CTL_FORMAT_MSK
#define ADXL372_FIFO_CTL_FORMAT_MODE(x)
#define ADXL372_FIFO_CTL_MODE_MSK
#define ADXL372_FIFO_CTL_MODE_MODE(x)
#define ADXL372_FIFO_CTL_SAMPLES_MSK
#define ADXL372_FIFO_CTL_SAMPLES_MODE(x)

/* ADXL372_STATUS_1 */
#define ADXL372_STATUS_1_DATA_RDY(x)
#define ADXL372_STATUS_1_FIFO_RDY(x)
#define ADXL372_STATUS_1_FIFO_FULL(x)
#define ADXL372_STATUS_1_FIFO_OVR(x)
#define ADXL372_STATUS_1_USR_NVM_BUSY(x)
#define ADXL372_STATUS_1_AWAKE(x)
#define ADXL372_STATUS_1_ERR_USR_REGS(x)

/* ADXL372_STATUS_2 */
#define ADXL372_STATUS_2_INACT(x)
#define ADXL372_STATUS_2_ACT(x)
#define ADXL372_STATUS_2_AC2(x)

/* ADXL372_INT1_MAP */
#define ADXL372_INT1_MAP_DATA_RDY_MSK
#define ADXL372_INT1_MAP_DATA_RDY_MODE(x)
#define ADXL372_INT1_MAP_FIFO_RDY_MSK
#define ADXL372_INT1_MAP_FIFO_RDY_MODE(x)
#define ADXL372_INT1_MAP_FIFO_FULL_MSK
#define ADXL372_INT1_MAP_FIFO_FULL_MODE(x)
#define ADXL372_INT1_MAP_FIFO_OVR_MSK
#define ADXL372_INT1_MAP_FIFO_OVR_MODE(x)
#define ADXL372_INT1_MAP_INACT_MSK
#define ADXL372_INT1_MAP_INACT_MODE(x)
#define ADXL372_INT1_MAP_ACT_MSK
#define ADXL372_INT1_MAP_ACT_MODE(x)
#define ADXL372_INT1_MAP_AWAKE_MSK
#define ADXL372_INT1_MAP_AWAKE_MODE(x)
#define ADXL372_INT1_MAP_LOW_MSK
#define ADXL372_INT1_MAP_LOW_MODE(x)

/* ADX372_THRESH */
#define ADXL372_THRESH_VAL_H_MSK
#define ADXL372_THRESH_VAL_H_SEL(x)
#define ADXL372_THRESH_VAL_L_MSK
#define ADXL372_THRESH_VAL_L_SEL(x)

/* The ADXL372 includes a deep, 512 sample FIFO buffer */
#define ADXL372_FIFO_SIZE
#define ADXL372_X_AXIS_EN(x)
#define ADXL372_Y_AXIS_EN(x)
#define ADXL372_Z_AXIS_EN(x)

/*
 * At +/- 200g with 12-bit resolution, scale is computed as:
 * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
 */
#define ADXL372_USCALE

enum adxl372_op_mode {};

enum adxl372_act_proc_mode {};

enum adxl372_th_activity {};

enum adxl372_odr {};

enum adxl372_bandwidth {};

static const unsigned int adxl372_th_reg_high_addr[3] =;

enum adxl372_fifo_format {};

enum adxl372_fifo_mode {};

static const int adxl372_samp_freq_tbl[5] =;

static const int adxl372_bw_freq_tbl[5] =;

struct adxl372_axis_lookup {};

static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] =;

static const struct iio_event_spec adxl372_events[] =;

#define ADXL372_ACCEL_CHANNEL(index, reg, axis)

static const struct iio_chan_spec adxl372_channels[] =;

struct adxl372_state {};

static const unsigned long adxl372_channel_masks[] =;

static ssize_t adxl372_read_threshold_value(struct iio_dev *indio_dev, unsigned int addr,
					    u16 *threshold)
{}

static ssize_t adxl372_write_threshold_value(struct iio_dev *indio_dev, unsigned int addr,
					     u16 threshold)
{}

static int adxl372_read_axis(struct adxl372_state *st, u8 addr)
{}

static int adxl372_set_op_mode(struct adxl372_state *st,
			       enum adxl372_op_mode op_mode)
{}

static int adxl372_set_odr(struct adxl372_state *st,
			   enum adxl372_odr odr)
{}

static int adxl372_find_closest_match(const int *array,
				      unsigned int size, int val)
{}

static int adxl372_set_bandwidth(struct adxl372_state *st,
				 enum adxl372_bandwidth bw)
{}

static int adxl372_set_act_proc_mode(struct adxl372_state *st,
				     enum adxl372_act_proc_mode mode)
{}

static int adxl372_set_activity_threshold(struct adxl372_state *st,
					  enum adxl372_th_activity act,
					  bool ref_en, bool enable,
					  unsigned int threshold)
{}

static int adxl372_set_activity_time_ms(struct adxl372_state *st,
					unsigned int act_time_ms)
{}

static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
					  unsigned int inact_time_ms)
{}

static int adxl372_set_interrupts(struct adxl372_state *st,
				  unsigned long int1_bitmask,
				  unsigned long int2_bitmask)
{}

static int adxl372_configure_fifo(struct adxl372_state *st)
{}

static int adxl372_get_status(struct adxl372_state *st,
			      u8 *status1, u8 *status2,
			      u16 *fifo_entries)
{}

static void adxl372_arrange_axis_data(struct adxl372_state *st, __be16 *sample)
{}

static void adxl372_push_event(struct iio_dev *indio_dev, s64 timestamp, u8 status2)
{}

static irqreturn_t adxl372_trigger_handler(int irq, void  *p)
{}

static int adxl372_setup(struct adxl372_state *st)
{}

static int adxl372_reg_access(struct iio_dev *indio_dev,
			      unsigned int reg,
			      unsigned int writeval,
			      unsigned int *readval)
{}

static int adxl372_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int *val, int *val2, long info)
{}

static int adxl372_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int val, int val2, long info)
{}

static int adxl372_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
				    enum iio_event_type type, enum iio_event_direction dir,
				    enum iio_event_info info, int *val, int *val2)
{}

static int adxl372_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
				     enum iio_event_type type, enum iio_event_direction dir,
				     enum iio_event_info info, int val, int val2)
{}

static int adxl372_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
				     enum iio_event_type type, enum iio_event_direction dir)
{}

static int adxl372_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
				      enum iio_event_type type, enum iio_event_direction dir,
				      int state)
{}

static ssize_t adxl372_show_filter_freq_avail(struct device *dev,
					      struct device_attribute *attr,
					      char *buf)
{}

static ssize_t adxl372_get_fifo_enabled(struct device *dev,
					  struct device_attribute *attr,
					  char *buf)
{}

static ssize_t adxl372_get_fifo_watermark(struct device *dev,
					  struct device_attribute *attr,
					  char *buf)
{}

IIO_STATIC_CONST_DEVICE_ATTR();
IIO_STATIC_CONST_DEVICE_ATTR();
static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
		       adxl372_get_fifo_watermark, NULL, 0);
static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
		       adxl372_get_fifo_enabled, NULL, 0);

static const struct iio_dev_attr *adxl372_fifo_attributes[] =;

static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val)
{}

static int adxl372_buffer_postenable(struct iio_dev *indio_dev)
{}

static int adxl372_buffer_predisable(struct iio_dev *indio_dev)
{}

static const struct iio_buffer_setup_ops adxl372_buffer_ops =;

static int adxl372_dready_trig_set_state(struct iio_trigger *trig,
					 bool state)
{}

static int adxl372_validate_trigger(struct iio_dev *indio_dev,
				    struct iio_trigger *trig)
{}

static const struct iio_trigger_ops adxl372_trigger_ops =;

static int adxl372_peak_dready_trig_set_state(struct iio_trigger *trig,
					      bool state)
{}

static const struct iio_trigger_ops adxl372_peak_data_trigger_ops =;

static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("400 800 1600 3200 6400");
static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
		       0444, adxl372_show_filter_freq_avail, NULL, 0);

static struct attribute *adxl372_attributes[] =;

static const struct attribute_group adxl372_attrs_group =;

static const struct iio_info adxl372_info =;

bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg)
{}
EXPORT_SYMBOL_NS_GPL();

int adxl372_probe(struct device *dev, struct regmap *regmap,
		  int irq, const char *name)
{}
EXPORT_SYMBOL_NS_GPL();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();