linux/include/dt-bindings/clock/qcom,gcc-mdm9607.h

/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
/*
 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
 */

#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H
#define _DT_BINDINGS_CLK_MSM_GCC_9607_H

#define GPLL0
#define GPLL0_EARLY
#define GPLL1
#define GPLL1_VOTE
#define GPLL2
#define GPLL2_EARLY
#define PCNOC_BFDCD_CLK_SRC
#define SYSTEM_NOC_BFDCD_CLK_SRC
#define GCC_SMMU_CFG_CLK
#define APSS_AHB_CLK_SRC
#define GCC_QDSS_DAP_CLK
#define BLSP1_QUP1_I2C_APPS_CLK_SRC
#define BLSP1_QUP1_SPI_APPS_CLK_SRC
#define BLSP1_QUP2_I2C_APPS_CLK_SRC
#define BLSP1_QUP2_SPI_APPS_CLK_SRC
#define BLSP1_QUP3_I2C_APPS_CLK_SRC
#define BLSP1_QUP3_SPI_APPS_CLK_SRC
#define BLSP1_QUP4_I2C_APPS_CLK_SRC
#define BLSP1_QUP4_SPI_APPS_CLK_SRC
#define BLSP1_QUP5_I2C_APPS_CLK_SRC
#define BLSP1_QUP5_SPI_APPS_CLK_SRC
#define BLSP1_QUP6_I2C_APPS_CLK_SRC
#define BLSP1_QUP6_SPI_APPS_CLK_SRC
#define BLSP1_UART1_APPS_CLK_SRC
#define BLSP1_UART2_APPS_CLK_SRC
#define CRYPTO_CLK_SRC
#define GP1_CLK_SRC
#define GP2_CLK_SRC
#define GP3_CLK_SRC
#define PDM2_CLK_SRC
#define SDCC1_APPS_CLK_SRC
#define SDCC2_APPS_CLK_SRC
#define APSS_TCU_CLK_SRC
#define USB_HS_SYSTEM_CLK_SRC
#define GCC_BLSP1_AHB_CLK
#define GCC_BLSP1_SLEEP_CLK
#define GCC_BLSP1_QUP1_I2C_APPS_CLK
#define GCC_BLSP1_QUP1_SPI_APPS_CLK
#define GCC_BLSP1_QUP2_I2C_APPS_CLK
#define GCC_BLSP1_QUP2_SPI_APPS_CLK
#define GCC_BLSP1_QUP3_I2C_APPS_CLK
#define GCC_BLSP1_QUP3_SPI_APPS_CLK
#define GCC_BLSP1_QUP4_I2C_APPS_CLK
#define GCC_BLSP1_QUP4_SPI_APPS_CLK
#define GCC_BLSP1_QUP5_I2C_APPS_CLK
#define GCC_BLSP1_QUP5_SPI_APPS_CLK
#define GCC_BLSP1_QUP6_I2C_APPS_CLK
#define GCC_BLSP1_QUP6_SPI_APPS_CLK
#define GCC_BLSP1_UART1_APPS_CLK
#define GCC_BLSP1_UART2_APPS_CLK
#define GCC_BOOT_ROM_AHB_CLK
#define GCC_CRYPTO_AHB_CLK
#define GCC_CRYPTO_AXI_CLK
#define GCC_CRYPTO_CLK
#define GCC_GP1_CLK
#define GCC_GP2_CLK
#define GCC_GP3_CLK
#define GCC_MSS_CFG_AHB_CLK
#define GCC_PDM2_CLK
#define GCC_PDM_AHB_CLK
#define GCC_PRNG_AHB_CLK
#define GCC_SDCC1_AHB_CLK
#define GCC_SDCC1_APPS_CLK
#define GCC_SDCC2_AHB_CLK
#define GCC_SDCC2_APPS_CLK
#define GCC_USB2A_PHY_SLEEP_CLK
#define GCC_USB_HS_AHB_CLK
#define GCC_USB_HS_SYSTEM_CLK
#define GCC_APSS_TCU_CLK
#define GCC_MSS_Q6_BIMC_AXI_CLK
#define BIMC_PLL
#define BIMC_PLL_VOTE
#define BIMC_DDR_CLK_SRC
#define BLSP1_UART3_APPS_CLK_SRC
#define BLSP1_UART4_APPS_CLK_SRC
#define BLSP1_UART5_APPS_CLK_SRC
#define BLSP1_UART6_APPS_CLK_SRC
#define GCC_BLSP1_UART3_APPS_CLK
#define GCC_BLSP1_UART4_APPS_CLK
#define GCC_BLSP1_UART5_APPS_CLK
#define GCC_BLSP1_UART6_APPS_CLK
#define GCC_APSS_AHB_CLK
#define GCC_APSS_AXI_CLK
#define GCC_USB_HS_PHY_CFG_AHB_CLK
#define GCC_USB_HSIC_CLK_SRC
#define GCC_USB_HSIC_IO_CAL_CLK_SRC
#define GCC_USB_HSIC_SYSTEM_CLK_SRC

/* Resets */
#define USB2_HS_PHY_ONLY_BCR
#define QUSB2_PHY_BCR
#define GCC_MSS_RESTART
#define USB_HS_HSIC_BCR
#define USB_HS_BCR

#endif