// SPDX-License-Identifier: GPL-2.0 /* * Amlogic Meson Successive Approximation Register (SAR) A/D Converter * * Copyright (C) 2017 Martin Blumenstingl <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/iio/iio.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/nvmem-consumer.h> #include <linux/interrupt.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/mfd/syscon.h> #define MESON_SAR_ADC_REG0 … #define MESON_SAR_ADC_REG0_PANEL_DETECT … #define MESON_SAR_ADC_REG0_BUSY_MASK … #define MESON_SAR_ADC_REG0_DELTA_BUSY … #define MESON_SAR_ADC_REG0_AVG_BUSY … #define MESON_SAR_ADC_REG0_SAMPLE_BUSY … #define MESON_SAR_ADC_REG0_FIFO_FULL … #define MESON_SAR_ADC_REG0_FIFO_EMPTY … #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK … #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK … #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK … #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL … #define MESON_SAR_ADC_REG0_SAMPLING_STOP … #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK … #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL … #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN … #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK … #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN … #define MESON_SAR_ADC_REG0_SAMPLING_START … #define MESON_SAR_ADC_REG0_CONTINUOUS_EN … #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE … #define MESON_SAR_ADC_CHAN_LIST … #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK … #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) … #define MESON_SAR_ADC_AVG_CNTL … #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) … #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) … #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) … #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) … #define MESON_SAR_ADC_REG3 … #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY … #define MESON_SAR_ADC_REG3_CLK_EN … #define MESON_SAR_ADC_REG3_BL30_INITIALIZED … #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN … #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE … #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK … #define MESON_SAR_ADC_REG3_DETECT_EN … #define MESON_SAR_ADC_REG3_ADC_EN … #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK … #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK … #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT … #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH … #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK … #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK … #define MESON_SAR_ADC_DELAY … #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK … #define MESON_SAR_ADC_DELAY_BL30_BUSY … #define MESON_SAR_ADC_DELAY_KERNEL_BUSY … #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK … #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK … #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK … #define MESON_SAR_ADC_LAST_RD … #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK … #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK … #define MESON_SAR_ADC_FIFO_RD … #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK … #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK … #define MESON_SAR_ADC_AUX_SW … #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) … #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX … #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX … #define MESON_SAR_ADC_AUX_SW_MODE_SEL … #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW … #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW … #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW … #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW … #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW … #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW … #define MESON_SAR_ADC_DELTA_10 … #define MESON_SAR_ADC_DELTA_10_TEMP_SEL … #define MESON_SAR_ADC_DELTA_10_TS_REVE1 … #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK … #define MESON_SAR_ADC_DELTA_10_TS_REVE0 … #define MESON_SAR_ADC_DELTA_10_TS_C_MASK … #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN … #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK … /* * NOTE: registers from here are undocumented (the vendor Linux kernel driver * and u-boot source served as reference). These only seem to be relevant on * GXBB and newer. */ #define MESON_SAR_ADC_REG11 … #define MESON_SAR_ADC_REG11_BANDGAP_EN … #define MESON_SAR_ADC_REG11_CMV_SEL … #define MESON_SAR_ADC_REG11_VREF_VOLTAGE … #define MESON_SAR_ADC_REG11_EOC … #define MESON_SAR_ADC_REG11_VREF_SEL … #define MESON_SAR_ADC_REG13 … #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK … #define MESON_SAR_ADC_MAX_FIFO_SIZE … #define MESON_SAR_ADC_TIMEOUT … #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL … #define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL … #define MESON_SAR_ADC_TEMP_OFFSET … /* temperature sensor calibration information in eFuse */ #define MESON_SAR_ADC_EFUSE_BYTES … #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL … #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED … #define MESON_HHI_DPLL_TOP_0 … #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 … /* for use with IIO_VAL_INT_PLUS_MICRO */ #define MILLION … #define MESON_SAR_ADC_CHAN(_chan) … #define MESON_SAR_ADC_TEMP_CHAN(_chan) … #define MESON_SAR_ADC_MUX(_chan, _sel) … enum meson_sar_adc_vref_sel { … }; enum meson_sar_adc_avg_mode { … }; enum meson_sar_adc_num_samples { … }; enum meson_sar_adc_chan7_mux_sel { … }; enum meson_sar_adc_channel_index { … }; static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = …; static const char * const chan7_mux_names[] = …; static const struct iio_chan_spec meson_sar_adc_iio_channels[] = …; static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = …; struct meson_sar_adc_param { … }; struct meson_sar_adc_data { … }; struct meson_sar_adc_priv { … }; static const struct regmap_config meson_sar_adc_regmap_config_gxbb = …; static const struct regmap_config meson_sar_adc_regmap_config_meson8 = …; static const struct iio_chan_spec * find_channel_by_num(struct iio_dev *indio_dev, int num) { … } static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) { … } static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) { … } static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) { … } static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, enum meson_sar_adc_chan7_mux_sel sel) { … } static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, int *val) { … } static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum meson_sar_adc_avg_mode mode, enum meson_sar_adc_num_samples samples) { … } static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) { … } static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev) { … } static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) { … } static int meson_sar_adc_lock(struct iio_dev *indio_dev) { … } static void meson_sar_adc_unlock(struct iio_dev *indio_dev) { … } static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev) { … } static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum meson_sar_adc_avg_mode avg_mode, enum meson_sar_adc_num_samples avg_samples, int *val) { … } static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, int *val, int *val2, long mask) { … } static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, void __iomem *base) { … } static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) { … } static int meson_sar_adc_init(struct iio_dev *indio_dev) { … } static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) { … } static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) { … } static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev) { … } static irqreturn_t meson_sar_adc_irq(int irq, void *data) { … } static int meson_sar_adc_calib(struct iio_dev *indio_dev) { … } static int read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, char *label) { … } static const struct iio_info meson_sar_adc_iio_info = …; static const struct meson_sar_adc_param meson_sar_adc_meson8_param = …; static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = …; static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = …; static const struct meson_sar_adc_param meson_sar_adc_gxl_param = …; static const struct meson_sar_adc_param meson_sar_adc_axg_param = …; static const struct meson_sar_adc_param meson_sar_adc_g12a_param = …; static const struct meson_sar_adc_data meson_sar_adc_meson8_data = …; static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = …; static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = …; static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = …; static const struct meson_sar_adc_data meson_sar_adc_gxl_data = …; static const struct meson_sar_adc_data meson_sar_adc_gxm_data = …; static const struct meson_sar_adc_data meson_sar_adc_axg_data = …; static const struct meson_sar_adc_data meson_sar_adc_g12a_data = …; static const struct of_device_id meson_sar_adc_of_match[] = …; MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match); static int meson_sar_adc_probe(struct platform_device *pdev) { … } static void meson_sar_adc_remove(struct platform_device *pdev) { … } static int meson_sar_adc_suspend(struct device *dev) { … } static int meson_sar_adc_resume(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, meson_sar_adc_suspend, meson_sar_adc_resume); static struct platform_driver meson_sar_adc_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux