linux/drivers/iio/dac/ad3552r.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Analog Devices AD3552R
 * Digital to Analog converter driver
 *
 * Copyright 2021 Analog Devices Inc.
 */
#include <asm/unaligned.h>
#include <linux/device.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>

/* Register addresses */
/* Primary address space */
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A
#define AD3552R_MASK_SOFTWARE_RESET
#define AD3552R_MASK_ADDR_ASCENSION
#define AD3552R_MASK_SDO_ACTIVE
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B
#define AD3552R_MASK_SINGLE_INST
#define AD3552R_MASK_SHORT_INSTRUCTION
#define AD3552R_REG_ADDR_DEVICE_CONFIG
#define AD3552R_MASK_DEVICE_STATUS(n)
#define AD3552R_MASK_CUSTOM_MODES
#define AD3552R_MASK_OPERATING_MODES
#define AD3552R_REG_ADDR_CHIP_TYPE
#define AD3552R_MASK_CLASS
#define AD3552R_REG_ADDR_PRODUCT_ID_L
#define AD3552R_REG_ADDR_PRODUCT_ID_H
#define AD3552R_REG_ADDR_CHIP_GRADE
#define AD3552R_MASK_GRADE
#define AD3552R_MASK_DEVICE_REVISION
#define AD3552R_REG_ADDR_SCRATCH_PAD
#define AD3552R_REG_ADDR_SPI_REVISION
#define AD3552R_REG_ADDR_VENDOR_L
#define AD3552R_REG_ADDR_VENDOR_H
#define AD3552R_REG_ADDR_STREAM_MODE
#define AD3552R_MASK_LENGTH
#define AD3552R_REG_ADDR_TRANSFER_REGISTER
#define AD3552R_MASK_MULTI_IO_MODE
#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C
#define AD3552R_MASK_CRC_ENABLE
#define AD3552R_MASK_STRICT_REGISTER_ACCESS
#define AD3552R_REG_ADDR_INTERFACE_STATUS_A
#define AD3552R_MASK_INTERFACE_NOT_READY
#define AD3552R_MASK_CLOCK_COUNTING_ERROR
#define AD3552R_MASK_INVALID_OR_NO_CRC
#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER
#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS
#define AD3552R_MASK_REGISTER_ADDRESS_INVALID
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D
#define AD3552R_MASK_ALERT_ENABLE_PULLUP
#define AD3552R_MASK_MEM_CRC_EN
#define AD3552R_MASK_SDO_DRIVE_STRENGTH
#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN
#define AD3552R_MASK_SPI_CONFIG_DDR
#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG
#define AD3552R_MASK_IDUMP_FAST_MODE
#define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN
#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM
#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE
#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL
#define AD3552R_REG_ADDR_ERR_ALARM_MASK
#define AD3552R_MASK_REF_RANGE_ALARM
#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM
#define AD3552R_MASK_MEM_CRC_ERR_ALARM
#define AD3552R_MASK_SPI_CRC_ERR_ALARM
#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM
#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM
#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM
#define AD3552R_REG_ADDR_ERR_STATUS
#define AD3552R_MASK_REF_RANGE_ERR_STATUS
#define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS
#define AD3552R_MASK_MEM_CRC_ERR_STATUS
#define AD3552R_MASK_RESET_STATUS
#define AD3552R_REG_ADDR_POWERDOWN_CONFIG
#define AD3552R_MASK_CH_DAC_POWERDOWN(ch)
#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch)
#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE
#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch)
#define AD3552R_REG_ADDR_CH_OFFSET(ch)
#define AD3552R_MASK_CH_OFFSET_BITS_0_7
#define AD3552R_REG_ADDR_CH_GAIN(ch)
#define AD3552R_MASK_CH_RANGE_OVERRIDE
#define AD3552R_MASK_CH_GAIN_SCALING_N
#define AD3552R_MASK_CH_GAIN_SCALING_P
#define AD3552R_MASK_CH_OFFSET_POLARITY
#define AD3552R_MASK_CH_OFFSET_BIT_8
/*
 * Secondary region
 * For multibyte registers specify the highest address because the access is
 * done in descending order
 */
#define AD3552R_SECONDARY_REGION_START
#define AD3552R_REG_ADDR_HW_LDAC_16B
#define AD3552R_REG_ADDR_CH_DAC_16B(ch)
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B
#define AD3552R_REG_ADDR_CH_SELECT_16B
#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B
#define AD3552R_REG_ADDR_SW_LDAC_16B
#define AD3552R_REG_ADDR_CH_INPUT_16B(ch)
/* 3 bytes registers */
#define AD3552R_REG_START_24B
#define AD3552R_REG_ADDR_HW_LDAC_24B
#define AD3552R_REG_ADDR_CH_DAC_24B(ch)
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B
#define AD3552R_REG_ADDR_CH_SELECT_24B
#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B
#define AD3552R_REG_ADDR_SW_LDAC_24B
#define AD3552R_REG_ADDR_CH_INPUT_24B(ch)

/* Useful defines */
#define AD3552R_MAX_CH
#define AD3552R_MASK_CH(ch)
#define AD3552R_MASK_ALL_CH
#define AD3552R_MAX_REG_SIZE
#define AD3552R_READ_BIT
#define AD3552R_ADDR_MASK
#define AD3552R_MASK_DAC_12B
#define AD3552R_DEFAULT_CONFIG_B_VALUE
#define AD3552R_SCRATCH_PAD_TEST_VAL1
#define AD3552R_SCRATCH_PAD_TEST_VAL2
#define AD3552R_GAIN_SCALE
#define AD3552R_LDAC_PULSE_US

enum ad3552r_ch_vref_select {};

enum ad3552r_id {};

enum ad3552r_ch_output_range {};

static const s32 ad3552r_ch_ranges[][2] =;

enum ad3542r_ch_output_range {};

static const s32 ad3542r_ch_ranges[][2] =;

enum ad3552r_ch_gain_scaling {};

/* Gain * AD3552R_GAIN_SCALE */
static const s32 gains_scaling_table[] =;

enum ad3552r_dev_attributes {};

enum ad3552r_ch_attributes {};

struct ad3552r_ch_data {};

struct ad3552r_model_data {};

struct ad3552r_desc {};

static const u16 addr_mask_map[][2] =;

/* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */
static const u16 addr_mask_map_ch[][3] =;

static u8 _ad3552r_reg_len(u8 addr)
{}

/* SPI transfer to device */
static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
			    u8 *data, bool is_read)
{}

static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
{}

static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
{}

static u16 ad3552r_field_prep(u16 val, u16 mask)
{}

/* Update field of a register, shift val if needed */
static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
				    u16 val)
{}

static int ad3552r_set_ch_value(struct ad3552r_desc *dac,
				enum ad3552r_ch_attributes attr,
				u8 ch,
				u16 val)
{}

#define AD3552R_CH_DAC(_idx)

static int ad3552r_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int *val,
			    int *val2,
			    long mask)
{}

static int ad3552r_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int val,
			     int val2,
			     long mask)
{}

static const struct iio_info ad3552r_iio_info =;

static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac)
{}

static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data)
{}

static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
{}

static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
{}

static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)
{}

struct reg_addr_pool {};

static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
{}

static int ad3552r_reset(struct ad3552r_desc *dac)
{}

static void ad3552r_get_custom_range(struct ad3552r_desc *dac, s32 i, s32 *v_min,
				     s32 *v_max)
{}

static void ad3552r_calc_gain_and_offset(struct ad3552r_desc *dac, s32 ch)
{}

static int ad3552r_find_range(const struct ad3552r_model_data *model_data,
			      s32 *vals)
{}

static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
					 struct fwnode_handle *child,
					 u32 ch)
{}

static int ad3552r_configure_device(struct ad3552r_desc *dac)
{}

static int ad3552r_init(struct ad3552r_desc *dac)
{}

static int ad3552r_probe(struct spi_device *spi)
{}

static const struct ad3552r_model_data ad3541r_model_data =;

static const struct ad3552r_model_data ad3542r_model_data =;

static const struct ad3552r_model_data ad3551r_model_data =;

static const struct ad3552r_model_data ad3552r_model_data =;

static const struct spi_device_id ad3552r_id[] =;
MODULE_DEVICE_TABLE(spi, ad3552r_id);

static const struct of_device_id ad3552r_of_match[] =;
MODULE_DEVICE_TABLE(of, ad3552r_of_match);

static struct spi_driver ad3552r_driver =;
module_spi_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();