// SPDX-License-Identifier: GPL-2.0-only /* * ADF4377 driver * * Copyright 2022 Analog Devices Inc. */ #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/gpio/consumer.h> #include <linux/module.h> #include <linux/notifier.h> #include <linux/property.h> #include <linux/spi/spi.h> #include <linux/iio/iio.h> #include <linux/regmap.h> #include <linux/units.h> #include <asm/unaligned.h> /* ADF4377 REG0000 Map */ #define ADF4377_0000_SOFT_RESET_R_MSK … #define ADF4377_0000_LSB_FIRST_R_MSK … #define ADF4377_0000_ADDRESS_ASC_R_MSK … #define ADF4377_0000_SDO_ACTIVE_R_MSK … #define ADF4377_0000_SDO_ACTIVE_MSK … #define ADF4377_0000_ADDRESS_ASC_MSK … #define ADF4377_0000_LSB_FIRST_MSK … #define ADF4377_0000_SOFT_RESET_MSK … /* ADF4377 REG0000 Bit Definition */ #define ADF4377_0000_SDO_ACTIVE_SPI_3W … #define ADF4377_0000_SDO_ACTIVE_SPI_4W … #define ADF4377_0000_ADDR_ASC_AUTO_DECR … #define ADF4377_0000_ADDR_ASC_AUTO_INCR … #define ADF4377_0000_LSB_FIRST_MSB … #define ADF4377_0000_LSB_FIRST_LSB … #define ADF4377_0000_SOFT_RESET_N_OP … #define ADF4377_0000_SOFT_RESET_EN … /* ADF4377 REG0001 Map */ #define ADF4377_0001_SINGLE_INSTR_MSK … #define ADF4377_0001_MASTER_RB_CTRL_MSK … /* ADF4377 REG0003 Bit Definition */ #define ADF4377_0003_CHIP_TYPE … /* ADF4377 REG0004 Bit Definition */ #define ADF4377_0004_PRODUCT_ID_LSB … /* ADF4377 REG0005 Bit Definition */ #define ADF4377_0005_PRODUCT_ID_MSB … /* ADF4377 REG000A Map */ #define ADF4377_000A_SCRATCHPAD_MSK … /* ADF4377 REG000C Bit Definition */ #define ADF4377_000C_VENDOR_ID_LSB … /* ADF4377 REG000D Bit Definition */ #define ADF4377_000D_VENDOR_ID_MSB … /* ADF4377 REG000F Bit Definition */ #define ADF4377_000F_R00F_RSV1_MSK … /* ADF4377 REG0010 Map*/ #define ADF4377_0010_N_INT_LSB_MSK … /* ADF4377 REG0011 Map*/ #define ADF4377_0011_EN_AUTOCAL_MSK … #define ADF4377_0011_EN_RDBLR_MSK … #define ADF4377_0011_DCLK_DIV2_MSK … #define ADF4377_0011_N_INT_MSB_MSK … /* ADF4377 REG0011 Bit Definition */ #define ADF4377_0011_DCLK_DIV2_1 … #define ADF4377_0011_DCLK_DIV2_2 … #define ADF4377_0011_DCLK_DIV2_4 … #define ADF4377_0011_DCLK_DIV2_8 … /* ADF4377 REG0012 Map*/ #define ADF4377_0012_CLKOUT_DIV_MSK … #define ADF4377_0012_R_DIV_MSK … /* ADF4377 REG0012 Bit Definition */ #define ADF4377_0012_CLKOUT_DIV_1 … #define ADF4377_0012_CLKOUT_DIV_2 … #define ADF4377_0012_CLKOUT_DIV_4 … #define ADF4377_0012_CLKOUT_DIV_8 … /* ADF4377 REG0013 Map */ #define ADF4377_0013_M_VCO_CORE_MSK … #define ADF4377_0013_VCO_BIAS_MSK … /* ADF4377 REG0013 Bit Definition */ #define ADF4377_0013_M_VCO_0 … #define ADF4377_0013_M_VCO_1 … #define ADF4377_0013_M_VCO_2 … #define ADF4377_0013_M_VCO_3 … /* ADF4377 REG0014 Map */ #define ADF4377_0014_M_VCO_BAND_MSK … /* ADF4377 REG0015 Map */ #define ADF4377_0015_BLEED_I_LSB_MSK … #define ADF4377_0015_BLEED_POL_MSK … #define ADF4377_0015_EN_BLEED_MSK … #define ADF4377_0015_CP_I_MSK … /* ADF4377 REG0015 Bit Definition */ #define ADF4377_CURRENT_SINK … #define ADF4377_CURRENT_SOURCE … #define ADF4377_0015_CP_0MA7 … #define ADF4377_0015_CP_0MA9 … #define ADF4377_0015_CP_1MA1 … #define ADF4377_0015_CP_1MA3 … #define ADF4377_0015_CP_1MA4 … #define ADF4377_0015_CP_1MA8 … #define ADF4377_0015_CP_2MA2 … #define ADF4377_0015_CP_2MA5 … #define ADF4377_0015_CP_2MA9 … #define ADF4377_0015_CP_3MA6 … #define ADF4377_0015_CP_4MA3 … #define ADF4377_0015_CP_5MA0 … #define ADF4377_0015_CP_5MA7 … #define ADF4377_0015_CP_7MA2 … #define ADF4377_0015_CP_8MA6 … #define ADF4377_0015_CP_10MA1 … /* ADF4377 REG0016 Map */ #define ADF4377_0016_BLEED_I_MSB_MSK … /* ADF4377 REG0017 Map */ #define ADF4377_0016_INV_CLKOUT_MSK … #define ADF4377_0016_N_DEL_MSK … /* ADF4377 REG0018 Map */ #define ADF4377_0018_CMOS_OV_MSK … #define ADF4377_0018_R_DEL_MSK … /* ADF4377 REG0018 Bit Definition */ #define ADF4377_0018_1V8_LOGIC … #define ADF4377_0018_3V3_LOGIC … /* ADF4377 REG0019 Map */ #define ADF4377_0019_CLKOUT2_OP_MSK … #define ADF4377_0019_CLKOUT1_OP_MSK … #define ADF4377_0019_PD_CLK_MSK … #define ADF4377_0019_PD_RDET_MSK … #define ADF4377_0019_PD_ADC_MSK … #define ADF4377_0019_PD_CALADC_MSK … /* ADF4377 REG0019 Bit Definition */ #define ADF4377_0019_CLKOUT_320MV … #define ADF4377_0019_CLKOUT_420MV … #define ADF4377_0019_CLKOUT_530MV … #define ADF4377_0019_CLKOUT_640MV … /* ADF4377 REG001A Map */ #define ADF4377_001A_PD_ALL_MSK … #define ADF4377_001A_PD_RDIV_MSK … #define ADF4377_001A_PD_NDIV_MSK … #define ADF4377_001A_PD_VCO_MSK … #define ADF4377_001A_PD_LD_MSK … #define ADF4377_001A_PD_PFDCP_MSK … #define ADF4377_001A_PD_CLKOUT1_MSK … #define ADF4377_001A_PD_CLKOUT2_MSK … /* ADF4377 REG001B Map */ #define ADF4377_001B_EN_LOL_MSK … #define ADF4377_001B_LDWIN_PW_MSK … #define ADF4377_001B_EN_LDWIN_MSK … #define ADF4377_001B_LD_COUNT_MSK … /* ADF4377 REG001B Bit Definition */ #define ADF4377_001B_LDWIN_PW_NARROW … #define ADF4377_001B_LDWIN_PW_WIDE … /* ADF4377 REG001C Map */ #define ADF4377_001C_EN_DNCLK_MSK … #define ADF4377_001C_EN_DRCLK_MSK … #define ADF4377_001C_RST_LD_MSK … #define ADF4377_001C_R01C_RSV1_MSK … /* ADF4377 REG001C Bit Definition */ #define ADF4377_001C_RST_LD_INACTIVE … #define ADF4377_001C_RST_LD_ACTIVE … #define ADF4377_001C_R01C_RSV1 … /* ADF4377 REG001D Map */ #define ADF4377_001D_MUXOUT_MSK … #define ADF4377_001D_EN_CPTEST_MSK … #define ADF4377_001D_CP_DOWN_MSK … #define ADF4377_001D_CP_UP_MSK … #define ADF4377_001D_EN_CPTEST_OFF … #define ADF4377_001D_EN_CPTEST_ON … #define ADF4377_001D_CP_DOWN_OFF … #define ADF4377_001D_CP_DOWN_ON … #define ADF4377_001D_CP_UP_OFF … #define ADF4377_001D_CP_UP_ON … /* ADF4377 REG001F Map */ #define ADF4377_001F_BST_REF_MSK … #define ADF4377_001F_FILT_REF_MSK … #define ADF4377_001F_REF_SEL_MSK … #define ADF4377_001F_R01F_RSV1_MSK … /* ADF4377 REG001F Bit Definition */ #define ADF4377_001F_BST_LARGE_REF_IN … #define ADF4377_001F_BST_SMALL_REF_IN … #define ADF4377_001F_FILT_REF_OFF … #define ADF4377_001F_FILT_REF_ON … #define ADF4377_001F_REF_SEL_DMA … #define ADF4377_001F_REF_SEL_LNA … #define ADF4377_001F_R01F_RSV1 … /* ADF4377 REG0020 Map */ #define ADF4377_0020_RST_SYS_MSK … #define ADF4377_0020_EN_ADC_CLK_MSK … #define ADF4377_0020_R020_RSV1_MSK … /* ADF4377 REG0021 Bit Definition */ #define ADF4377_0021_R021_RSV1 … /* ADF4377 REG0022 Bit Definition */ #define ADF4377_0022_R022_RSV1 … /* ADF4377 REG0023 Map */ #define ADF4377_0023_CAT_CT_SEL … #define ADF4377_0023_R023_RSV1_MSK … /* ADF4377 REG0023 Bit Definition */ #define ADF4377_0023_R023_RSV1 … /* ADF4377 REG0024 Map */ #define ADF4377_0024_DCLK_MODE_MSK … /* ADF4377 REG0025 Map */ #define ADF4377_0025_CLKODIV_DB_MSK … #define ADF4377_0025_DCLK_DB_MSK … #define ADF4377_0025_R025_RSV1_MSK … /* ADF4377 REG0025 Bit Definition */ #define ADF4377_0025_R025_RSV1 … /* ADF4377 REG0026 Map */ #define ADF4377_0026_VCO_BAND_DIV_MSK … /* ADF4377 REG0027 Map */ #define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK … /* ADF4377 REG0028 Map */ #define ADF4377_0028_O_VCO_DB_MSK … #define ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK … /* ADF4377 REG0029 Map */ #define ADF4377_0029_VCO_ALC_TO_LSB_MSK … /* ADF4377 REG002A Map */ #define ADF4377_002A_DEL_CTRL_DB_MSK … #define ADF4377_002A_VCO_ALC_TO_MSB_MSK … /* ADF4377 REG002C Map */ #define ADF4377_002C_R02C_RSV1 … /* ADF4377 REG002D Map */ #define ADF4377_002D_ADC_CLK_DIV_MSK … /* ADF4377 REG002E Map */ #define ADF4377_002E_EN_ADC_CNV_MSK … #define ADF4377_002E_EN_ADC_MSK … #define ADF4377_002E_ADC_A_CONV_MSK … /* ADF4377 REG002E Bit Definition */ #define ADF4377_002E_ADC_A_CONV_ADC_ST_CNV … #define ADF4377_002E_ADC_A_CONV_VCO_CALIB … /* ADF4377 REG002F Map */ #define ADF4377_002F_DCLK_DIV1_MSK … /* ADF4377 REG002F Bit Definition */ #define ADF4377_002F_DCLK_DIV1_1 … #define ADF4377_002F_DCLK_DIV1_2 … #define ADF4377_002F_DCLK_DIV1_8 … #define ADF4377_002F_DCLK_DIV1_32 … /* ADF4377 REG0031 Bit Definition */ #define ADF4377_0031_R031_RSV1 … /* ADF4377 REG0032 Map */ #define ADF4377_0032_ADC_CLK_SEL_MSK … #define ADF4377_0032_R032_RSV1_MSK … /* ADF4377 REG0032 Bit Definition */ #define ADF4377_0032_ADC_CLK_SEL_N_OP … #define ADF4377_0032_ADC_CLK_SEL_SPI_CLK … #define ADF4377_0032_R032_RSV1 … /* ADF4377 REG0033 Bit Definition */ #define ADF4377_0033_R033_RSV1 … /* ADF4377 REG0034 Bit Definition */ #define ADF4377_0034_R034_RSV1 … /* ADF4377 REG003A Bit Definition */ #define ADF4377_003A_R03A_RSV1 … /* ADF4377 REG003B Bit Definition */ #define ADF4377_003B_R03B_RSV1 … /* ADF4377 REG003D Map */ #define ADF4377_003D_O_VCO_BAND_MSK … #define ADF4377_003D_O_VCO_CORE_MSK … #define ADF4377_003D_O_VCO_BIAS_MSK … /* ADF4377 REG003D Bit Definition */ #define ADF4377_003D_O_VCO_BAND_VCO_CALIB … #define ADF4377_003D_O_VCO_BAND_M_VCO … #define ADF4377_003D_O_VCO_CORE_VCO_CALIB … #define ADF4377_003D_O_VCO_CORE_M_VCO … #define ADF4377_003D_O_VCO_BIAS_VCO_CALIB … #define ADF4377_003D_O_VCO_BIAS_M_VCO … /* ADF4377 REG0042 Map */ #define ADF4377_0042_R042_RSV1 … /* ADF4377 REG0045 Map */ #define ADF4377_0045_ADC_ST_CNV_MSK … /* ADF4377 REG0049 Map */ #define ADF4377_0049_EN_CLK2_MSK … #define ADF4377_0049_EN_CLK1_MSK … #define ADF4377_0049_REF_OK_MSK … #define ADF4377_0049_ADC_BUSY_MSK … #define ADF4377_0049_FSM_BUSY_MSK … #define ADF4377_0049_LOCKED_MSK … /* ADF4377 REG004B Map */ #define ADF4377_004B_VCO_CORE_MSK … /* ADF4377 REG004C Map */ #define ADF4377_004C_CHIP_TEMP_LSB_MSK … /* ADF4377 REG004D Map */ #define ADF4377_004D_CHIP_TEMP_MSB_MSK … /* ADF4377 REG004F Map */ #define ADF4377_004F_VCO_BAND_MSK … /* ADF4377 REG0051 Map */ #define ADF4377_0051_VCO_BIAS_MSK … /* ADF4377 REG0054 Map */ #define ADF4377_0054_CHIP_VERSION_MSK … /* Specifications */ #define ADF4377_SPI_READ_CMD … #define ADF4377_MAX_VCO_FREQ … #define ADF4377_MIN_VCO_FREQ … #define ADF4377_MAX_REFIN_FREQ … #define ADF4377_MIN_REFIN_FREQ … #define ADF4377_MAX_FREQ_PFD … #define ADF4377_MIN_FREQ_PFD … #define ADF4377_MAX_CLKPN_FREQ … #define ADF4377_MIN_CLKPN_FREQ … #define ADF4377_FREQ_PFD_80MHZ … #define ADF4377_FREQ_PFD_125MHZ … #define ADF4377_FREQ_PFD_160MHZ … #define ADF4377_FREQ_PFD_250MHZ … #define ADF4377_FREQ_PFD_320MHZ … enum { … }; enum muxout_select_mode { … }; struct adf4377_state { … }; static const char * const adf4377_muxout_modes[] = …; static const struct reg_sequence adf4377_reg_defaults[] = …; static const struct regmap_config adf4377_regmap_config = …; static int adf4377_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int write_val, unsigned int *read_val) { … } static const struct iio_info adf4377_info = …; static int adf4377_soft_reset(struct adf4377_state *st) { … } static int adf4377_get_freq(struct adf4377_state *st, u64 *freq) { … } static int adf4377_set_freq(struct adf4377_state *st, u64 freq) { … } static void adf4377_gpio_init(struct adf4377_state *st) { … } static int adf4377_init(struct adf4377_state *st) { … } static ssize_t adf4377_read(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, char *buf) { … } static ssize_t adf4377_write(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, const char *buf, size_t len) { … } #define _ADF4377_EXT_INFO(_name, _shared, _ident) … static const struct iio_chan_spec_ext_info adf4377_ext_info[] = …; static const struct iio_chan_spec adf4377_channels[] = …; static int adf4377_properties_parse(struct adf4377_state *st) { … } static int adf4377_freq_change(struct notifier_block *nb, unsigned long action, void *data) { … } static int adf4377_probe(struct spi_device *spi) { … } static const struct spi_device_id adf4377_id[] = …; MODULE_DEVICE_TABLE(spi, adf4377_id); static const struct of_device_id adf4377_of_match[] = …; MODULE_DEVICE_TABLE(of, adf4377_of_match); static struct spi_driver adf4377_driver = …; module_spi_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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