/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2020 Invensense, Inc. */ #ifndef INV_ICM42600_H_ #define INV_ICM42600_H_ #include <linux/bits.h> #include <linux/bitfield.h> #include <linux/regmap.h> #include <linux/mutex.h> #include <linux/regulator/consumer.h> #include <linux/pm.h> #include <linux/iio/iio.h> #include <linux/iio/common/inv_sensors_timestamp.h> #include "inv_icm42600_buffer.h" enum inv_icm42600_chip { … }; /* serial bus slew rates */ enum inv_icm42600_slew_rate { … }; enum inv_icm42600_sensor_mode { … }; /* gyroscope fullscale values */ enum inv_icm42600_gyro_fs { … }; enum inv_icm42686_gyro_fs { … }; /* accelerometer fullscale values */ enum inv_icm42600_accel_fs { … }; enum inv_icm42686_accel_fs { … }; /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ enum inv_icm42600_odr { … }; enum inv_icm42600_filter { … }; struct inv_icm42600_sensor_conf { … }; #define INV_ICM42600_SENSOR_CONF_INIT … struct inv_icm42600_conf { … }; struct inv_icm42600_suspended { … }; /** * struct inv_icm42600_state - driver state variables * @lock: lock for serializing multiple registers access. * @chip: chip identifier. * @name: chip name. * @map: regmap pointer. * @vdd_supply: VDD voltage regulator for the chip. * @vddio_supply: I/O voltage regulator for the chip. * @orientation: sensor chip orientation relative to main hardware. * @conf: chip sensors configurations. * @suspended: suspended sensors configuration. * @indio_gyro: gyroscope IIO device. * @indio_accel: accelerometer IIO device. * @buffer: data transfer buffer aligned for DMA. * @fifo: FIFO management structure. * @timestamp: interrupt timestamps. */ struct inv_icm42600_state { … }; /** * struct inv_icm42600_sensor_state - sensor state variables * @scales: table of scales. * @scales_len: length (nb of items) of the scales table. * @power_mode: sensor requested power mode (for common frequencies) * @filter: sensor filter. * @ts: timestamp module states. */ struct inv_icm42600_sensor_state { … }; /* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */ /* Bank selection register, available in all banks */ #define INV_ICM42600_REG_BANK_SEL … #define INV_ICM42600_BANK_SEL_MASK … /* User bank 0 (MSB 0x00) */ #define INV_ICM42600_REG_DEVICE_CONFIG … #define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET … #define INV_ICM42600_REG_DRIVE_CONFIG … #define INV_ICM42600_DRIVE_CONFIG_I2C_MASK … #define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) … #define INV_ICM42600_DRIVE_CONFIG_SPI_MASK … #define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) … #define INV_ICM42600_REG_INT_CONFIG … #define INV_ICM42600_INT_CONFIG_INT2_LATCHED … #define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL … #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH … #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW … #define INV_ICM42600_INT_CONFIG_INT1_LATCHED … #define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL … #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH … #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW … #define INV_ICM42600_REG_FIFO_CONFIG … #define INV_ICM42600_FIFO_CONFIG_MASK … #define INV_ICM42600_FIFO_CONFIG_BYPASS … #define INV_ICM42600_FIFO_CONFIG_STREAM … #define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL … /* all sensor data are 16 bits (2 registers wide) in big-endian */ #define INV_ICM42600_REG_TEMP_DATA … #define INV_ICM42600_REG_ACCEL_DATA_X … #define INV_ICM42600_REG_ACCEL_DATA_Y … #define INV_ICM42600_REG_ACCEL_DATA_Z … #define INV_ICM42600_REG_GYRO_DATA_X … #define INV_ICM42600_REG_GYRO_DATA_Y … #define INV_ICM42600_REG_GYRO_DATA_Z … #define INV_ICM42600_DATA_INVALID … #define INV_ICM42600_REG_INT_STATUS … #define INV_ICM42600_INT_STATUS_UI_FSYNC … #define INV_ICM42600_INT_STATUS_PLL_RDY … #define INV_ICM42600_INT_STATUS_RESET_DONE … #define INV_ICM42600_INT_STATUS_DATA_RDY … #define INV_ICM42600_INT_STATUS_FIFO_THS … #define INV_ICM42600_INT_STATUS_FIFO_FULL … #define INV_ICM42600_INT_STATUS_AGC_RDY … /* * FIFO access registers * FIFO count is 16 bits (2 registers) big-endian * FIFO data is a continuous read register to read FIFO content */ #define INV_ICM42600_REG_FIFO_COUNT … #define INV_ICM42600_REG_FIFO_DATA … #define INV_ICM42600_REG_SIGNAL_PATH_RESET … #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN … #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET … #define INV_ICM42600_SIGNAL_PATH_RESET_RESET … #define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE … #define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH … /* default configuration: all data big-endian and fifo count in bytes */ #define INV_ICM42600_REG_INTF_CONFIG0 … #define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA … #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC … #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN … #define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN … #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK … #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS … #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS … #define INV_ICM42600_REG_INTF_CONFIG1 … #define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC … #define INV_ICM42600_REG_PWR_MGMT0 … #define INV_ICM42600_PWR_MGMT0_TEMP_DIS … #define INV_ICM42600_PWR_MGMT0_IDLE … #define INV_ICM42600_PWR_MGMT0_GYRO(_mode) … #define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) … #define INV_ICM42600_REG_GYRO_CONFIG0 … #define INV_ICM42600_GYRO_CONFIG0_FS(_fs) … #define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) … #define INV_ICM42600_REG_ACCEL_CONFIG0 … #define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) … #define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) … #define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 … #define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) … #define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) … #define INV_ICM42600_REG_TMST_CONFIG … #define INV_ICM42600_TMST_CONFIG_MASK … #define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN … #define INV_ICM42600_TMST_CONFIG_TMST_RES_16US … #define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN … #define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN … #define INV_ICM42600_TMST_CONFIG_TMST_EN … #define INV_ICM42600_REG_FIFO_CONFIG1 … #define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD … #define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH … #define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN … #define INV_ICM42600_FIFO_CONFIG1_TEMP_EN … #define INV_ICM42600_FIFO_CONFIG1_GYRO_EN … #define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN … /* FIFO watermark is 16 bits (2 registers wide) in little-endian */ #define INV_ICM42600_REG_FIFO_WATERMARK … #define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) … /* FIFO is 2048 bytes, let 12 samples for reading latency */ #define INV_ICM42600_FIFO_WATERMARK_MAX … #define INV_ICM42600_REG_INT_CONFIG1 … #define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION … #define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE … #define INV_ICM42600_INT_CONFIG1_ASYNC_RESET … #define INV_ICM42600_REG_INT_SOURCE0 … #define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN … #define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN … #define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN … #define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN … #define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN … #define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN … #define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN … #define INV_ICM42600_REG_WHOAMI … #define INV_ICM42600_WHOAMI_ICM42600 … #define INV_ICM42600_WHOAMI_ICM42602 … #define INV_ICM42600_WHOAMI_ICM42605 … #define INV_ICM42600_WHOAMI_ICM42686 … #define INV_ICM42600_WHOAMI_ICM42622 … #define INV_ICM42600_WHOAMI_ICM42688 … #define INV_ICM42600_WHOAMI_ICM42631 … /* User bank 1 (MSB 0x10) */ #define INV_ICM42600_REG_SENSOR_CONFIG0 … #define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE … #define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE … #define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE … #define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE … #define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE … #define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE … /* Timestamp value is 20 bits (3 registers) in little-endian */ #define INV_ICM42600_REG_TMSTVAL … #define INV_ICM42600_TMSTVAL_MASK … #define INV_ICM42600_REG_INTF_CONFIG4 … #define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY … #define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE … #define INV_ICM42600_REG_INTF_CONFIG6 … #define INV_ICM42600_INTF_CONFIG6_MASK … #define INV_ICM42600_INTF_CONFIG6_I3C_EN … #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN … #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN … #define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN … #define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN … /* User bank 4 (MSB 0x40) */ #define INV_ICM42600_REG_INT_SOURCE8 … #define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN … #define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN … #define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN … #define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN … #define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN … #define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN … #define INV_ICM42600_REG_OFFSET_USER0 … #define INV_ICM42600_REG_OFFSET_USER1 … #define INV_ICM42600_REG_OFFSET_USER2 … #define INV_ICM42600_REG_OFFSET_USER3 … #define INV_ICM42600_REG_OFFSET_USER4 … #define INV_ICM42600_REG_OFFSET_USER5 … #define INV_ICM42600_REG_OFFSET_USER6 … #define INV_ICM42600_REG_OFFSET_USER7 … #define INV_ICM42600_REG_OFFSET_USER8 … /* Sleep times required by the driver */ #define INV_ICM42600_POWER_UP_TIME_MS … #define INV_ICM42600_RESET_TIME_MS … #define INV_ICM42600_ACCEL_STARTUP_TIME_MS … #define INV_ICM42600_GYRO_STARTUP_TIME_MS … #define INV_ICM42600_GYRO_STOP_TIME_MS … #define INV_ICM42600_TEMP_STARTUP_TIME_MS … #define INV_ICM42600_SUSPEND_DELAY_MS … inv_icm42600_bus_setup; extern const struct regmap_config inv_icm42600_regmap_config; extern const struct dev_pm_ops inv_icm42600_pm_ops; const struct iio_mount_matrix * inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev, const struct iio_chan_spec *chan); uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr); int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st, struct inv_icm42600_sensor_conf *conf, unsigned int *sleep_ms); int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st, struct inv_icm42600_sensor_conf *conf, unsigned int *sleep_ms); int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable, unsigned int *sleep_ms); int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval); int inv_icm42600_core_probe(struct regmap *regmap, int chip, int irq, inv_icm42600_bus_setup bus_setup); struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st); int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev); struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st); int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev); #endif
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