ntb_hw_gen4.h | Explore in Territory

/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)          */
/* Copyright(c) 2020 Intel Corporation. All rights reserved.   */
#ifndef _NTB_INTEL_GEN4_H_
#define _NTB_INTEL_GEN4_H_

#include "ntb_hw_intel.h"

/* Supported PCI device revision range for ICX */
#define PCI_DEVICE_REVISION_ICX_MIN …
#define PCI_DEVICE_REVISION_ICX_MAX …

/* Intel Gen4 NTB hardware */
/* PCIe config space */
#define GEN4_IMBAR23SZ_OFFSET …
#define GEN4_IMBAR45SZ_OFFSET …
#define GEN4_EMBAR23SZ_OFFSET …
#define GEN4_EMBAR45SZ_OFFSET …
#define GEN4_DEVCTRL_OFFSET …
#define GEN4_DEVSTS_OFFSET …
#define GEN4_UNCERRSTS_OFFSET …
#define GEN4_CORERRSTS_OFFSET …

/* BAR0 MMIO */
#define GEN4_NTBCNTL_OFFSET …
#define GEN4_IM23XBASE_OFFSET …
#define GEN4_IM23XLMT_OFFSET …
#define GEN4_IM45XBASE_OFFSET …
#define GEN4_IM45XLMT_OFFSET …
#define GEN4_IM_INT_STATUS_OFFSET …
#define GEN4_IM_INT_DISABLE_OFFSET …
#define GEN4_INTVEC_OFFSET …
#define GEN4_IM23XBASEIDX_OFFSET …
#define GEN4_IM45XBASEIDX_OFFSET …
#define GEN4_IM_SPAD_OFFSET …
#define GEN4_IM_SPAD_SEM_OFFSET …
#define GEN4_IM_SPAD_STICKY_OFFSET …
#define GEN4_IM_DOORBELL_OFFSET …
#define GEN4_LTR_SWSEL_OFFSET …
#define GEN4_LTR_ACTIVE_OFFSET …
#define GEN4_LTR_IDLE_OFFSET …
#define GEN4_EM_SPAD_OFFSET …
/* note, link status is now in MMIO and not config space for NTB */
#define GEN4_LINK_CTRL_OFFSET …
#define GEN4_LINK_STATUS_OFFSET …
#define GEN4_PPD0_OFFSET …
#define GEN4_PPD1_OFFSET …
#define GEN4_LTSSMSTATEJMP …

#define GEN4_PPD_CLEAR_TRN …
#define GEN4_PPD_LINKTRN …
#define GEN4_PPD_CONN_MASK …
#define SPR_PPD_CONN_MASK …
#define GEN4_PPD_CONN_B2B …
#define GEN4_PPD_DEV_MASK …
#define GEN4_PPD_DEV_DSD …
#define GEN4_PPD_DEV_USD …
#define SPR_PPD_DEV_MASK …
#define SPR_PPD_DEV_DSD …
#define SPR_PPD_DEV_USD …
#define GEN4_LINK_CTRL_LINK_DISABLE …

#define GEN4_SLOTSTS …
#define GEN4_SLOTSTS_DLLSCS …

#define GEN4_PPD_TOPO_MASK …
#define GEN4_PPD_TOPO_B2B_USD …
#define GEN4_PPD_TOPO_B2B_DSD …

#define SPR_PPD_TOPO_MASK …
#define SPR_PPD_TOPO_B2B_USD …
#define SPR_PPD_TOPO_B2B_DSD …

#define GEN4_DB_COUNT …
#define GEN4_DB_LINK …
#define GEN4_DB_LINK_BIT …
#define GEN4_DB_MSIX_VECTOR_COUNT …
#define GEN4_DB_MSIX_VECTOR_SHIFT …
#define GEN4_DB_TOTAL_SHIFT …
#define GEN4_SPAD_COUNT …

#define NTB_CTL_E2I_BAR23_SNOOP …
#define NTB_CTL_E2I_BAR23_NOSNOOP …
#define NTB_CTL_I2E_BAR23_SNOOP …
#define NTB_CTL_I2E_BAR23_NOSNOOP …
#define NTB_CTL_E2I_BAR45_SNOOP …
#define NTB_CTL_E2I_BAR45_NOSNOO …
#define NTB_CTL_I2E_BAR45_SNOOP …
#define NTB_CTL_I2E_BAR45_NOSNOOP …
#define NTB_CTL_BUSNO_DIS_INC …
#define NTB_CTL_LINK_DOWN …

#define NTB_SJC_FORCEDETECT …

#define NTB_LTR_SWSEL_ACTIVE …
#define NTB_LTR_SWSEL_IDLE …

#define NTB_LTR_NS_SHIFT …
#define NTB_LTR_ACTIVE_VAL …
#define NTB_LTR_ACTIVE_LATSCALE …
#define NTB_LTR_ACTIVE_REQMNT …

#define NTB_LTR_IDLE_VAL …
#define NTB_LTR_IDLE_LATSCALE …
#define NTB_LTR_IDLE_REQMNT …

ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
				      size_t count, loff_t *offp);
int gen4_init_dev(struct intel_ntb_dev *ndev);
ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
				      size_t count, loff_t *offp);

extern const struct ntb_dev_ops intel_ntb4_ops;

static inline int pdev_is_ICX(struct pci_dev *pdev)
{ … }

static inline int pdev_is_SPR(struct pci_dev *pdev)
{ … }

#endif
linux/drivers/ntb/hw/intel/ntb_hw_gen4.h
