// SPDX-License-Identifier: GPL-2.0-only /* * ARM DMC-620 memory controller PMU driver * * Copyright (C) 2020 Ampere Computing LLC. */ #define DMC620_PMUNAME … #define DMC620_DRVNAME … #define pr_fmt(fmt) … #include <linux/acpi.h> #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/cpuhotplug.h> #include <linux/cpumask.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/perf_event.h> #include <linux/platform_device.h> #include <linux/printk.h> #include <linux/rculist.h> #include <linux/refcount.h> #define DMC620_PA_SHIFT … #define DMC620_CNT_INIT … #define DMC620_CNT_MAX_PERIOD … #define DMC620_PMU_CLKDIV2_MAX_COUNTERS … #define DMC620_PMU_CLK_MAX_COUNTERS … #define DMC620_PMU_MAX_COUNTERS … /* * The PMU registers start at 0xA00 in the DMC-620 memory map, and these * offsets are relative to that base. * * Each counter has a group of control/value registers, and the * DMC620_PMU_COUNTERn offsets are within a counter group. * * The counter registers groups start at 0xA10. */ #define DMC620_PMU_OVERFLOW_STATUS_CLKDIV2 … #define DMC620_PMU_OVERFLOW_STATUS_CLKDIV2_MASK … #define DMC620_PMU_OVERFLOW_STATUS_CLK … #define DMC620_PMU_OVERFLOW_STATUS_CLK_MASK … #define DMC620_PMU_COUNTERS_BASE … #define DMC620_PMU_COUNTERn_MASK_31_00 … #define DMC620_PMU_COUNTERn_MASK_63_32 … #define DMC620_PMU_COUNTERn_MATCH_31_00 … #define DMC620_PMU_COUNTERn_MATCH_63_32 … #define DMC620_PMU_COUNTERn_CONTROL … #define DMC620_PMU_COUNTERn_CONTROL_ENABLE … #define DMC620_PMU_COUNTERn_CONTROL_INVERT … #define DMC620_PMU_COUNTERn_CONTROL_EVENT_MUX … #define DMC620_PMU_COUNTERn_CONTROL_INCR_MUX … #define DMC620_PMU_COUNTERn_VALUE … /* Offset of the registers for a given counter, relative to 0xA00 */ #define DMC620_PMU_COUNTERn_OFFSET(n) … /* * dmc620_pmu_irqs_lock: protects dmc620_pmu_irqs list * dmc620_pmu_node_lock: protects pmus_node lists in all dmc620_pmu instances */ static DEFINE_MUTEX(dmc620_pmu_irqs_lock); static DEFINE_MUTEX(dmc620_pmu_node_lock); static LIST_HEAD(dmc620_pmu_irqs); struct dmc620_pmu_irq { … }; struct dmc620_pmu { … }; #define to_dmc620_pmu(p) … static int cpuhp_state_num; struct dmc620_pmu_event_attr { … }; static ssize_t dmc620_pmu_event_show(struct device *dev, struct device_attribute *attr, char *page) { … } #define DMC620_PMU_EVENT_ATTR(_name, _eventid, _clkdiv2) … static struct attribute *dmc620_pmu_events_attrs[] = …; static const struct attribute_group dmc620_pmu_events_attr_group = …; /* User ABI */ #define ATTR_CFG_FLD_mask_CFG … #define ATTR_CFG_FLD_mask_LO … #define ATTR_CFG_FLD_mask_HI … #define ATTR_CFG_FLD_match_CFG … #define ATTR_CFG_FLD_match_LO … #define ATTR_CFG_FLD_match_HI … #define ATTR_CFG_FLD_invert_CFG … #define ATTR_CFG_FLD_invert_LO … #define ATTR_CFG_FLD_invert_HI … #define ATTR_CFG_FLD_incr_CFG … #define ATTR_CFG_FLD_incr_LO … #define ATTR_CFG_FLD_incr_HI … #define ATTR_CFG_FLD_event_CFG … #define ATTR_CFG_FLD_event_LO … #define ATTR_CFG_FLD_event_HI … #define ATTR_CFG_FLD_clkdiv2_CFG … #define ATTR_CFG_FLD_clkdiv2_LO … #define ATTR_CFG_FLD_clkdiv2_HI … #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) … #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) … #define GEN_PMU_FORMAT_ATTR(name) … #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) … #define ATTR_CFG_GET_FLD(attr, name) … GEN_PMU_FORMAT_ATTR(…); GEN_PMU_FORMAT_ATTR(…); GEN_PMU_FORMAT_ATTR(…); GEN_PMU_FORMAT_ATTR(…); GEN_PMU_FORMAT_ATTR(…); GEN_PMU_FORMAT_ATTR(…); static struct attribute *dmc620_pmu_formats_attrs[] = …; static const struct attribute_group dmc620_pmu_format_attr_group = …; static ssize_t dmc620_pmu_cpumask_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static struct device_attribute dmc620_pmu_cpumask_attr = …; static struct attribute *dmc620_pmu_cpumask_attrs[] = …; static const struct attribute_group dmc620_pmu_cpumask_attr_group = …; static const struct attribute_group *dmc620_pmu_attr_groups[] = …; static inline u32 dmc620_pmu_creg_read(struct dmc620_pmu *dmc620_pmu, unsigned int idx, unsigned int reg) { … } static inline void dmc620_pmu_creg_write(struct dmc620_pmu *dmc620_pmu, unsigned int idx, unsigned int reg, u32 val) { … } static unsigned int dmc620_event_to_counter_control(struct perf_event *event) { … } static int dmc620_get_event_idx(struct perf_event *event) { … } static inline u64 dmc620_pmu_read_counter(struct perf_event *event) { … } static void dmc620_pmu_event_update(struct perf_event *event) { … } static void dmc620_pmu_event_set_period(struct perf_event *event) { … } static void dmc620_pmu_enable_counter(struct perf_event *event) { … } static void dmc620_pmu_disable_counter(struct perf_event *event) { … } static irqreturn_t dmc620_pmu_handle_irq(int irq_num, void *data) { … } static struct dmc620_pmu_irq *__dmc620_pmu_get_irq(int irq_num) { … } static int dmc620_pmu_get_irq(struct dmc620_pmu *dmc620_pmu, int irq_num) { … } static void dmc620_pmu_put_irq(struct dmc620_pmu *dmc620_pmu) { … } static int dmc620_pmu_event_init(struct perf_event *event) { … } static void dmc620_pmu_read(struct perf_event *event) { … } static void dmc620_pmu_start(struct perf_event *event, int flags) { … } static void dmc620_pmu_stop(struct perf_event *event, int flags) { … } static int dmc620_pmu_add(struct perf_event *event, int flags) { … } static void dmc620_pmu_del(struct perf_event *event, int flags) { … } static int dmc620_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node) { … } static int dmc620_pmu_device_probe(struct platform_device *pdev) { … } static void dmc620_pmu_device_remove(struct platform_device *pdev) { … } static const struct acpi_device_id dmc620_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, dmc620_acpi_match); static struct platform_driver dmc620_pmu_driver = …; static int __init dmc620_pmu_init(void) { … } static void __exit dmc620_pmu_exit(void) { … } module_init(…) …; module_exit(dmc620_pmu_exit); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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