// SPDX-License-Identifier: GPL-2.0 /* Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver * * Copyright (C) 2021 Marvell. */ #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/perf_event.h> #include <linux/hrtimer.h> #include <linux/acpi.h> #include <linux/platform_device.h> /* Performance Counters Operating Mode Control Registers */ #define DDRC_PERF_CNT_OP_MODE_CTRL … #define OP_MODE_CTRL_VAL_MANNUAL … /* Performance Counters Start Operation Control Registers */ #define DDRC_PERF_CNT_START_OP_CTRL … #define START_OP_CTRL_VAL_START … #define START_OP_CTRL_VAL_ACTIVE … /* Performance Counters End Operation Control Registers */ #define DDRC_PERF_CNT_END_OP_CTRL … #define END_OP_CTRL_VAL_END … /* Performance Counters End Status Registers */ #define DDRC_PERF_CNT_END_STATUS … #define END_STATUS_VAL_END_TIMER_MODE_END … /* Performance Counters Configuration Registers */ #define DDRC_PERF_CFG_BASE … /* 8 Generic event counter + 2 fixed event counters */ #define DDRC_PERF_NUM_GEN_COUNTERS … #define DDRC_PERF_NUM_FIX_COUNTERS … #define DDRC_PERF_READ_COUNTER_IDX … #define DDRC_PERF_WRITE_COUNTER_IDX … #define DDRC_PERF_NUM_COUNTERS … /* Generic event counter registers */ #define DDRC_PERF_CFG(n) … #define EVENT_ENABLE … /* Two dedicated event counters for DDR reads and writes */ #define EVENT_DDR_READS … #define EVENT_DDR_WRITES … /* * programmable events IDs in programmable event counters. * DO NOT change these event-id numbers, they are used to * program event bitmap in h/w. */ #define EVENT_OP_IS_ZQLATCH … #define EVENT_OP_IS_ZQSTART … #define EVENT_OP_IS_TCR_MRR … #define EVENT_OP_IS_DQSOSC_MRR … #define EVENT_OP_IS_DQSOSC_MPC … #define EVENT_VISIBLE_WIN_LIMIT_REACHED_WR … #define EVENT_VISIBLE_WIN_LIMIT_REACHED_RD … #define EVENT_BSM_STARVATION … #define EVENT_BSM_ALLOC … #define EVENT_LPR_REQ_WITH_NOCREDIT … #define EVENT_HPR_REQ_WITH_NOCREDIT … #define EVENT_OP_IS_ZQCS … #define EVENT_OP_IS_ZQCL … #define EVENT_OP_IS_LOAD_MODE … #define EVENT_OP_IS_SPEC_REF … #define EVENT_OP_IS_CRIT_REF … #define EVENT_OP_IS_REFRESH … #define EVENT_OP_IS_ENTER_MPSM … #define EVENT_OP_IS_ENTER_POWERDOWN … #define EVENT_OP_IS_ENTER_SELFREF … #define EVENT_WAW_HAZARD … #define EVENT_RAW_HAZARD … #define EVENT_WAR_HAZARD … #define EVENT_WRITE_COMBINE … #define EVENT_RDWR_TRANSITIONS … #define EVENT_PRECHARGE_FOR_OTHER … #define EVENT_PRECHARGE_FOR_RDWR … #define EVENT_OP_IS_PRECHARGE … #define EVENT_OP_IS_MWR … #define EVENT_OP_IS_WR … #define EVENT_OP_IS_RD … #define EVENT_OP_IS_RD_ACTIVATE … #define EVENT_OP_IS_RD_OR_WR … #define EVENT_OP_IS_ACTIVATE … #define EVENT_WR_XACT_WHEN_CRITICAL … #define EVENT_LPR_XACT_WHEN_CRITICAL … #define EVENT_HPR_XACT_WHEN_CRITICAL … #define EVENT_DFI_RD_DATA_CYCLES … #define EVENT_DFI_WR_DATA_CYCLES … #define EVENT_ACT_BYPASS … #define EVENT_READ_BYPASS … #define EVENT_HIF_HI_PRI_RD … #define EVENT_HIF_RMW … #define EVENT_HIF_RD … #define EVENT_HIF_WR … #define EVENT_HIF_RD_OR_WR … /* Event counter value registers */ #define DDRC_PERF_CNT_VALUE_BASE … #define DDRC_PERF_CNT_VALUE(n) … /* Fixed event counter enable/disable register */ #define DDRC_PERF_CNT_FREERUN_EN … #define DDRC_PERF_FREERUN_WRITE_EN … #define DDRC_PERF_FREERUN_READ_EN … /* Fixed event counter control register */ #define DDRC_PERF_CNT_FREERUN_CTRL … #define DDRC_FREERUN_WRITE_CNT_CLR … #define DDRC_FREERUN_READ_CNT_CLR … /* Fixed event counter value register */ #define DDRC_PERF_CNT_VALUE_WR_OP … #define DDRC_PERF_CNT_VALUE_RD_OP … #define DDRC_PERF_CNT_VALUE_OVERFLOW … #define DDRC_PERF_CNT_MAX_VALUE … struct cn10k_ddr_pmu { … }; #define to_cn10k_ddr_pmu(p) … static ssize_t cn10k_ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, char *page) { … } #define CN10K_DDR_PMU_EVENT_ATTR(_name, _id) … static struct attribute *cn10k_ddr_perf_events_attrs[] = …; static struct attribute_group cn10k_ddr_perf_events_attr_group = …; PMU_FORMAT_ATTR(…); static struct attribute *cn10k_ddr_perf_format_attrs[] = …; static struct attribute_group cn10k_ddr_perf_format_attr_group = …; static ssize_t cn10k_ddr_perf_cpumask_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static struct device_attribute cn10k_ddr_perf_cpumask_attr = …; static struct attribute *cn10k_ddr_perf_cpumask_attrs[] = …; static struct attribute_group cn10k_ddr_perf_cpumask_attr_group = …; static const struct attribute_group *cn10k_attr_groups[] = …; /* Default poll timeout is 100 sec, which is very sufficient for * 48 bit counter incremented max at 5.6 GT/s, which may take many * hours to overflow. */ static unsigned long cn10k_ddr_pmu_poll_period_sec = …; module_param_named(poll_period_sec, cn10k_ddr_pmu_poll_period_sec, ulong, 0644); static ktime_t cn10k_ddr_pmu_timer_period(void) { … } static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap) { … } static int cn10k_ddr_perf_alloc_counter(struct cn10k_ddr_pmu *pmu, struct perf_event *event) { … } static void cn10k_ddr_perf_free_counter(struct cn10k_ddr_pmu *pmu, int counter) { … } static int cn10k_ddr_perf_event_init(struct perf_event *event) { … } static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu, int counter, bool enable) { … } static u64 cn10k_ddr_perf_read_counter(struct cn10k_ddr_pmu *pmu, int counter) { … } static void cn10k_ddr_perf_event_update(struct perf_event *event) { … } static void cn10k_ddr_perf_event_start(struct perf_event *event, int flags) { … } static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags) { … } static void cn10k_ddr_perf_event_stop(struct perf_event *event, int flags) { … } static void cn10k_ddr_perf_event_del(struct perf_event *event, int flags) { … } static void cn10k_ddr_perf_pmu_enable(struct pmu *pmu) { … } static void cn10k_ddr_perf_pmu_disable(struct pmu *pmu) { … } static void cn10k_ddr_perf_event_update_all(struct cn10k_ddr_pmu *pmu) { … } static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pmu) { … } static enum hrtimer_restart cn10k_ddr_pmu_timer_handler(struct hrtimer *hrtimer) { … } static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) { … } static int cn10k_ddr_perf_probe(struct platform_device *pdev) { … } static void cn10k_ddr_perf_remove(struct platform_device *pdev) { … } #ifdef CONFIG_OF static const struct of_device_id cn10k_ddr_pmu_of_match[] = …; MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); #endif #ifdef CONFIG_ACPI static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match); #endif static struct platform_driver cn10k_ddr_pmu_driver = …; static int __init cn10k_ddr_pmu_init(void) { … } static void __exit cn10k_ddr_pmu_exit(void) { … } module_init(…) …; module_exit(cn10k_ddr_pmu_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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