linux/drivers/thunderbolt/nhi.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Thunderbolt driver - NHI driver
 *
 * Copyright (c) 2014 Andreas Noever <[email protected]>
 * Copyright (C) 2018, Intel Corporation
 */

#ifndef DSL3510_H_
#define DSL3510_H_

#include <linux/thunderbolt.h>

enum nhi_fw_mode { … };

enum nhi_mailbox_cmd { … };

int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);

/**
 * struct tb_nhi_ops - NHI specific optional operations
 * @init: NHI specific initialization
 * @suspend_noirq: NHI specific suspend_noirq hook
 * @resume_noirq: NHI specific resume_noirq hook
 * @runtime_suspend: NHI specific runtime_suspend hook
 * @runtime_resume: NHI specific runtime_resume hook
 * @shutdown: NHI specific shutdown
 */
struct tb_nhi_ops { … };

extern const struct tb_nhi_ops icl_nhi_ops;

/*
 * PCI IDs used in this driver from Win Ridge forward. There is no
 * need for the PCI quirk anymore as we will use ICM also on Apple
 * hardware.
 */
#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI …
#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI …
#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI …
#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI …
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI …
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE …
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI …
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE …
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI …
#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE …
#define PCI_DEVICE_ID_INTEL_ADL_NHI0 …
#define PCI_DEVICE_ID_INTEL_ADL_NHI1 …
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI …
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI …
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE …
#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE …
#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 …
#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 …
#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 …
#define PCI_DEVICE_ID_INTEL_ICL_NHI1 …
#define PCI_DEVICE_ID_INTEL_ICL_NHI0 …
#define PCI_DEVICE_ID_INTEL_TGL_NHI0 …
#define PCI_DEVICE_ID_INTEL_TGL_NHI1 …
#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 …
#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 …
#define PCI_DEVICE_ID_INTEL_RPL_NHI0 …
#define PCI_DEVICE_ID_INTEL_RPL_NHI1 …
#define PCI_DEVICE_ID_INTEL_LNL_NHI0 …
#define PCI_DEVICE_ID_INTEL_LNL_NHI1 …

#define PCI_CLASS_SERIAL_USB_USB4 …

#endif