/* SPDX-License-Identifier: GPL-2.0 */ /* * Thunderbolt driver - Port/Switch config area registers * * Every thunderbolt device consists (logically) of a switch with multiple * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, * COUNTERS) which are used to configure the device. * * Copyright (c) 2014 Andreas Noever <[email protected]> * Copyright (C) 2018, Intel Corporation */ #ifndef _TB_REGS #define _TB_REGS #include <linux/types.h> #define TB_ROUTE_SHIFT … /* * TODO: should be 63? But we do not know how to receive frames larger than 256 * bytes at the frame level. (header + checksum = 16, 60*4 = 240) */ #define TB_MAX_CONFIG_RW_LENGTH … enum tb_switch_cap { … }; enum tb_switch_vse_cap { … }; enum tb_port_cap { … }; enum tb_port_state { … }; /* capability headers */ struct tb_cap_basic { … } __packed; /** * struct tb_cap_extended_short - Switch extended short capability * @next: Pointer to the next capability. If @next and @length are zero * then we have a long cap. * @cap: Base capability ID (see &enum tb_switch_cap) * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap) * @length: Length of this capability */ struct tb_cap_extended_short { … } __packed; /** * struct tb_cap_extended_long - Switch extended long capability * @zero1: This field should be zero * @cap: Base capability ID (see &enum tb_switch_cap) * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap) * @zero2: This field should be zero * @next: Pointer to the next capability * @length: Length of this capability */ struct tb_cap_extended_long { … } __packed; /** * struct tb_cap_any - Structure capable of hold every capability * @basic: Basic capability * @extended_short: Vendor specific capability * @extended_long: Vendor specific extended capability */ struct tb_cap_any { … } __packed; /* capabilities */ struct tb_cap_link_controller { … } __packed; struct tb_cap_phy { … } __packed; struct tb_eeprom_ctl { … } __packed; struct tb_cap_plug_events { … } __packed; /* device headers */ /* Present on port 0 in TB_CFG_SWITCH at address zero. */ struct tb_regs_switch_header { … } __packed; /* Used with the router thunderbolt_version */ #define USB4_VERSION_MAJOR_MASK … #define ROUTER_CS_1 … #define ROUTER_CS_3 … #define ROUTER_CS_3_V … #define ROUTER_CS_4 … /* Used with the router cmuv field */ #define ROUTER_CS_4_CMUV_V1 … #define ROUTER_CS_4_CMUV_V2 … #define ROUTER_CS_5 … #define ROUTER_CS_5_SLP … #define ROUTER_CS_5_WOP … #define ROUTER_CS_5_WOU … #define ROUTER_CS_5_WOD … #define ROUTER_CS_5_CNS … #define ROUTER_CS_5_PTO … #define ROUTER_CS_5_UTO … #define ROUTER_CS_5_HCO … #define ROUTER_CS_5_CV … #define ROUTER_CS_6 … #define ROUTER_CS_6_SLPR … #define ROUTER_CS_6_TNS … #define ROUTER_CS_6_WOPS … #define ROUTER_CS_6_WOUS … #define ROUTER_CS_6_HCI … #define ROUTER_CS_6_CR … #define ROUTER_CS_7 … #define ROUTER_CS_9 … #define ROUTER_CS_25 … #define ROUTER_CS_26 … #define ROUTER_CS_26_OPCODE_MASK … #define ROUTER_CS_26_STATUS_MASK … #define ROUTER_CS_26_STATUS_SHIFT … #define ROUTER_CS_26_ONS … #define ROUTER_CS_26_OV … /* USB4 router operations opcodes */ enum usb4_switch_op { … }; /* Router TMU configuration */ #define TMU_RTR_CS_0 … #define TMU_RTR_CS_0_FREQ_WIND_MASK … #define TMU_RTR_CS_0_TD … #define TMU_RTR_CS_0_UCAP … #define TMU_RTR_CS_1 … #define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK … #define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT … #define TMU_RTR_CS_2 … #define TMU_RTR_CS_3 … #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK … #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK … #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT … #define TMU_RTR_CS_15 … #define TMU_RTR_CS_15_FREQ_AVG_MASK … #define TMU_RTR_CS_15_DELAY_AVG_MASK … #define TMU_RTR_CS_15_OFFSET_AVG_MASK … #define TMU_RTR_CS_15_ERROR_AVG_MASK … #define TMU_RTR_CS_18 … #define TMU_RTR_CS_18_DELTA_AVG_CONST_MASK … #define TMU_RTR_CS_22 … #define TMU_RTR_CS_24 … #define TMU_RTR_CS_25 … enum tb_port_type { … }; /* Present on every port in TB_CF_PORT at address zero. */ struct tb_regs_port_header { … } __packed; /* Basic adapter configuration registers */ #define ADP_CS_4 … #define ADP_CS_4_NFC_BUFFERS_MASK … #define ADP_CS_4_TOTAL_BUFFERS_MASK … #define ADP_CS_4_TOTAL_BUFFERS_SHIFT … #define ADP_CS_4_LCK … #define ADP_CS_5 … #define ADP_CS_5_LCA_MASK … #define ADP_CS_5_LCA_SHIFT … #define ADP_CS_5_DHP … /* TMU adapter registers */ #define TMU_ADP_CS_3 … #define TMU_ADP_CS_3_UDM … #define TMU_ADP_CS_6 … #define TMU_ADP_CS_6_DTS … #define TMU_ADP_CS_8 … #define TMU_ADP_CS_8_REPL_TIMEOUT_MASK … #define TMU_ADP_CS_8_EUDM … #define TMU_ADP_CS_8_REPL_THRESHOLD_MASK … #define TMU_ADP_CS_9 … #define TMU_ADP_CS_9_REPL_N_MASK … #define TMU_ADP_CS_9_DIRSWITCH_N_MASK … #define TMU_ADP_CS_9_ADP_TS_INTERVAL_MASK … /* Lane adapter registers */ #define LANE_ADP_CS_0 … #define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK … #define LANE_ADP_CS_0_SUPPORTED_SPEED_SHIFT … #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK … #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT … #define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL … #define LANE_ADP_CS_0_CL0S_SUPPORT … #define LANE_ADP_CS_0_CL1_SUPPORT … #define LANE_ADP_CS_0_CL2_SUPPORT … #define LANE_ADP_CS_1 … #define LANE_ADP_CS_1_TARGET_SPEED_MASK … #define LANE_ADP_CS_1_TARGET_SPEED_GEN3 … #define LANE_ADP_CS_1_TARGET_WIDTH_MASK … #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT … #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE … #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL … #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK … #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX … #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX … #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL … #define LANE_ADP_CS_1_CL0S_ENABLE … #define LANE_ADP_CS_1_CL1_ENABLE … #define LANE_ADP_CS_1_CL2_ENABLE … #define LANE_ADP_CS_1_LD … #define LANE_ADP_CS_1_LB … #define LANE_ADP_CS_1_CURRENT_SPEED_MASK … #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT … #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 … #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 … #define LANE_ADP_CS_1_CURRENT_SPEED_GEN4 … #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK … #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT … #define LANE_ADP_CS_1_PMS … /* USB4 port registers */ #define PORT_CS_1 … #define PORT_CS_1_LENGTH_SHIFT … #define PORT_CS_1_TARGET_MASK … #define PORT_CS_1_TARGET_SHIFT … #define PORT_CS_1_RETIMER_INDEX_SHIFT … #define PORT_CS_1_WNR_WRITE … #define PORT_CS_1_NR … #define PORT_CS_1_RC … #define PORT_CS_1_PND … #define PORT_CS_2 … #define PORT_CS_18 … #define PORT_CS_18_BE … #define PORT_CS_18_TCM … #define PORT_CS_18_CPS … #define PORT_CS_18_WOCS … #define PORT_CS_18_WODS … #define PORT_CS_18_WOU4S … #define PORT_CS_18_CSA … #define PORT_CS_18_TIP … #define PORT_CS_19 … #define PORT_CS_19_DPR … #define PORT_CS_19_PC … #define PORT_CS_19_PID … #define PORT_CS_19_WOC … #define PORT_CS_19_WOD … #define PORT_CS_19_WOU4 … #define PORT_CS_19_START_ASYM … /* Display Port adapter registers */ #define ADP_DP_CS_0 … #define ADP_DP_CS_0_VIDEO_HOPID_MASK … #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT … #define ADP_DP_CS_0_AE … #define ADP_DP_CS_0_VE … #define ADP_DP_CS_1_AUX_TX_HOPID_MASK … #define ADP_DP_CS_1_AUX_RX_HOPID_MASK … #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT … #define ADP_DP_CS_2 … #define ADP_DP_CS_2_NRD_MLC_MASK … #define ADP_DP_CS_2_HPD … #define ADP_DP_CS_2_NRD_MLR_MASK … #define ADP_DP_CS_2_NRD_MLR_SHIFT … #define ADP_DP_CS_2_CA … #define ADP_DP_CS_2_GR_MASK … #define ADP_DP_CS_2_GR_SHIFT … #define ADP_DP_CS_2_GR_0_25G … #define ADP_DP_CS_2_GR_0_5G … #define ADP_DP_CS_2_GR_1G … #define ADP_DP_CS_2_GROUP_ID_MASK … #define ADP_DP_CS_2_GROUP_ID_SHIFT … #define ADP_DP_CS_2_CM_ID_MASK … #define ADP_DP_CS_2_CM_ID_SHIFT … #define ADP_DP_CS_2_CMMS … #define ADP_DP_CS_2_ESTIMATED_BW_MASK … #define ADP_DP_CS_2_ESTIMATED_BW_SHIFT … #define ADP_DP_CS_3 … #define ADP_DP_CS_3_HPDC … #define DP_LOCAL_CAP … #define DP_REMOTE_CAP … /* For DP IN adapter */ #define DP_STATUS … #define DP_STATUS_ALLOCATED_BW_MASK … #define DP_STATUS_ALLOCATED_BW_SHIFT … /* For DP OUT adapter */ #define DP_STATUS_CTRL … #define DP_STATUS_CTRL_CMHS … #define DP_STATUS_CTRL_UF … #define DP_COMMON_CAP … /* Only if DP IN supports BW allocation mode */ #define ADP_DP_CS_8 … #define ADP_DP_CS_8_REQUESTED_BW_MASK … #define ADP_DP_CS_8_DPME … #define ADP_DP_CS_8_DR … /* * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP * with exception of DPRX done. */ #define DP_COMMON_CAP_RATE_MASK … #define DP_COMMON_CAP_RATE_SHIFT … #define DP_COMMON_CAP_RATE_RBR … #define DP_COMMON_CAP_RATE_HBR … #define DP_COMMON_CAP_RATE_HBR2 … #define DP_COMMON_CAP_RATE_HBR3 … #define DP_COMMON_CAP_LANES_MASK … #define DP_COMMON_CAP_LANES_SHIFT … #define DP_COMMON_CAP_1_LANE … #define DP_COMMON_CAP_2_LANES … #define DP_COMMON_CAP_4_LANES … #define DP_COMMON_CAP_UHBR10 … #define DP_COMMON_CAP_UHBR20 … #define DP_COMMON_CAP_UHBR13_5 … #define DP_COMMON_CAP_LTTPR_NS … #define DP_COMMON_CAP_BW_MODE … #define DP_COMMON_CAP_DPRX_DONE … /* Only present if DP IN supports BW allocation mode */ #define ADP_DP_CS_8 … #define ADP_DP_CS_8_DPME … #define ADP_DP_CS_8_DR … /* PCIe adapter registers */ #define ADP_PCIE_CS_0 … #define ADP_PCIE_CS_0_PE … #define ADP_PCIE_CS_1 … #define ADP_PCIE_CS_1_EE … /* USB adapter registers */ #define ADP_USB3_CS_0 … #define ADP_USB3_CS_0_V … #define ADP_USB3_CS_0_PE … #define ADP_USB3_CS_1 … #define ADP_USB3_CS_1_CUBW_MASK … #define ADP_USB3_CS_1_CDBW_MASK … #define ADP_USB3_CS_1_CDBW_SHIFT … #define ADP_USB3_CS_1_HCA … #define ADP_USB3_CS_2 … #define ADP_USB3_CS_2_AUBW_MASK … #define ADP_USB3_CS_2_ADBW_MASK … #define ADP_USB3_CS_2_ADBW_SHIFT … #define ADP_USB3_CS_2_CMR … #define ADP_USB3_CS_3 … #define ADP_USB3_CS_3_SCALE_MASK … #define ADP_USB3_CS_4 … #define ADP_USB3_CS_4_MSLR_MASK … #define ADP_USB3_CS_4_MSLR_SHIFT … #define ADP_USB3_CS_4_MSLR_20G … /* Hop register from TB_CFG_HOPS. 8 byte per entry. */ struct tb_regs_hop { … } __packed; /* TMU Thunderbolt 3 registers */ #define TB_TIME_VSEC_3_CS_9 … #define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK … #define TB_TIME_VSEC_3_CS_26 … #define TB_TIME_VSEC_3_CS_26_TD … /* * Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6 * (see above) as in USB4 spec, but these specific bits used for Titan Ridge * only and reserved in USB4 spec. */ #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK … #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 … #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 … /* Plug Events registers */ #define TB_PLUG_EVENTS_USB_DISABLE … #define TB_PLUG_EVENTS_CS_1_LANE_DISABLE … #define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE … #define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE … #define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE … #define TB_PLUG_EVENTS_PCIE_WR_DATA … #define TB_PLUG_EVENTS_PCIE_CMD … #define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK … #define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT … #define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK … #define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK … #define TB_PLUG_EVENTS_PCIE_CMD_WR … #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT … #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK … #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL … #define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK … #define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK … #define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA … /* CP Low Power registers */ #define TB_LOW_PWR_C1_CL1 … #define TB_LOW_PWR_C1_CL1_OBJ_MASK … #define TB_LOW_PWR_C1_CL2_OBJ_MASK … #define TB_LOW_PWR_C1_PORT_A_MASK … #define TB_LOW_PWR_C0_PORT_B_MASK … #define TB_LOW_PWR_C3_CL1 … /* Common link controller registers */ #define TB_LC_DESC … #define TB_LC_DESC_NLC_MASK … #define TB_LC_DESC_SIZE_SHIFT … #define TB_LC_DESC_SIZE_MASK … #define TB_LC_DESC_PORT_SIZE_SHIFT … #define TB_LC_DESC_PORT_SIZE_MASK … #define TB_LC_FUSE … #define TB_LC_SNK_ALLOCATION … #define TB_LC_SNK_ALLOCATION_SNK0_MASK … #define TB_LC_SNK_ALLOCATION_SNK0_CM … #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT … #define TB_LC_SNK_ALLOCATION_SNK1_MASK … #define TB_LC_SNK_ALLOCATION_SNK1_CM … #define TB_LC_POWER … /* Link controller registers */ #define TB_LC_PORT_MODE … #define TB_LC_PORT_MODE_DPR … #define TB_LC_CS_42 … #define TB_LC_CS_42_USB_PLUGGED … #define TB_LC_PORT_ATTR … #define TB_LC_PORT_ATTR_BE … #define TB_LC_SX_CTRL … #define TB_LC_SX_CTRL_WOC … #define TB_LC_SX_CTRL_WOD … #define TB_LC_SX_CTRL_WODPC … #define TB_LC_SX_CTRL_WODPD … #define TB_LC_SX_CTRL_WOU4 … #define TB_LC_SX_CTRL_WOP … #define TB_LC_SX_CTRL_L1C … #define TB_LC_SX_CTRL_L1D … #define TB_LC_SX_CTRL_L2C … #define TB_LC_SX_CTRL_L2D … #define TB_LC_SX_CTRL_SLI … #define TB_LC_SX_CTRL_UPSTREAM … #define TB_LC_SX_CTRL_SLP … #define TB_LC_LINK_ATTR … #define TB_LC_LINK_ATTR_CPS … #define TB_LC_LINK_REQ … #define TB_LC_LINK_REQ_XHCI_CONNECT … #endif
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