/* SPDX-License-Identifier: GPL-2.0 */ /* * Thunderbolt driver - NHI registers * * Copyright (c) 2014 Andreas Noever <[email protected]> * Copyright (C) 2018, Intel Corporation */ #ifndef NHI_REGS_H_ #define NHI_REGS_H_ #include <linux/types.h> enum ring_flags { … }; /** * struct ring_desc - TX/RX ring entry * * For TX set length/eof/sof. * For RX length/eof/sof are set by the NHI. */ struct ring_desc { … } __packed; /* NHI registers in bar 0 */ /* * 16 bytes per entry, one entry for every hop (REG_CAPS) * 00: physical pointer to an array of struct ring_desc * 08: ring tail (set by NHI) * 10: ring head (index of first non posted descriptor) * 12: descriptor count */ #define REG_TX_RING_BASE … /* * 16 bytes per entry, one entry for every hop (REG_CAPS) * 00: physical pointer to an array of struct ring_desc * 08: ring head (index of first not posted descriptor) * 10: ring tail (set by NHI) * 12: descriptor count * 14: max frame sizes (anything larger than 0x100 has no effect) */ #define REG_RX_RING_BASE … /* * 32 bytes per entry, one entry for every hop (REG_CAPS) * 00: enum_ring_flags * 04: isoch time stamp ?? (write 0) * ..: unknown */ #define REG_TX_OPTIONS_BASE … /* * 32 bytes per entry, one entry for every hop (REG_CAPS) * 00: enum ring_flags * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to * the corresponding TX hop id. * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings) * ..: unknown */ #define REG_RX_OPTIONS_BASE … #define REG_RX_OPTIONS_E2E_HOP_MASK … #define REG_RX_OPTIONS_E2E_HOP_SHIFT … /* * three bitfields: tx, rx, rx overflow * Every bitfield contains one bit for every hop (REG_CAPS). * New interrupts are fired only after ALL registers have been * read (even those containing only disabled rings). */ #define REG_RING_NOTIFY_BASE … #define RING_NOTIFY_REG_COUNT(nhi) … #define REG_RING_INT_CLEAR … /* * two bitfields: rx, tx * Both bitfields contains one bit for every hop (REG_CAPS). To * enable/disable interrupts set/clear the corresponding bits. */ #define REG_RING_INTERRUPT_BASE … #define RING_INTERRUPT_REG_COUNT(nhi) … #define REG_RING_INTERRUPT_MASK_CLEAR_BASE … #define REG_INT_THROTTLING_RATE … /* Interrupt Vector Allocation */ #define REG_INT_VEC_ALLOC_BASE … #define REG_INT_VEC_ALLOC_BITS … #define REG_INT_VEC_ALLOC_MASK … #define REG_INT_VEC_ALLOC_REGS … /* The last 11 bits contain the number of hops supported by the NHI port. */ #define REG_CAPS … #define REG_CAPS_VERSION_MASK … #define REG_CAPS_VERSION_2 … #define REG_DMA_MISC … #define REG_DMA_MISC_INT_AUTO_CLEAR … #define REG_DMA_MISC_DISABLE_AUTO_CLEAR … #define REG_RESET … #define REG_RESET_HRR … #define REG_INMAIL_DATA … #define REG_INMAIL_CMD … #define REG_INMAIL_CMD_MASK … #define REG_INMAIL_ERROR … #define REG_INMAIL_OP_REQUEST … #define REG_OUTMAIL_CMD … #define REG_OUTMAIL_CMD_OPMODE_SHIFT … #define REG_OUTMAIL_CMD_OPMODE_MASK … #define REG_FW_STS … #define REG_FW_STS_NVM_AUTH_DONE … #define REG_FW_STS_CIO_RESET_REQ … #define REG_FW_STS_ICM_EN_CPU … #define REG_FW_STS_ICM_EN_INVERT … #define REG_FW_STS_ICM_EN … /* ICL NHI VSEC registers */ /* FW ready */ #define VS_CAP_9 … #define VS_CAP_9_FW_READY … /* UUID */ #define VS_CAP_10 … #define VS_CAP_11 … /* LTR */ #define VS_CAP_15 … #define VS_CAP_16 … /* TBT2PCIe */ #define VS_CAP_18 … #define VS_CAP_18_DONE … /* PCIe2TBT */ #define VS_CAP_19 … #define VS_CAP_19_VALID … #define VS_CAP_19_CMD_SHIFT … #define VS_CAP_19_CMD_MASK … /* Force power */ #define VS_CAP_22 … #define VS_CAP_22_FORCE_POWER … #define VS_CAP_22_DMA_DELAY_MASK … #define VS_CAP_22_DMA_DELAY_SHIFT … /** * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands * @ICL_LC_GO2SX: Ask LC to enter Sx without wake * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset */ enum icl_lc_mailbox_cmd { … }; #endif
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