// SPDX-License-Identifier: GPL-2.0 /* * FPGA Manager Driver for Altera SOCFPGA * * Copyright (C) 2013-2015 Altera Corporation */ #include <linux/completion.h> #include <linux/delay.h> #include <linux/fpga/fpga-mgr.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/pm.h> /* Register offsets */ #define SOCFPGA_FPGMGR_STAT_OFST … #define SOCFPGA_FPGMGR_CTL_OFST … #define SOCFPGA_FPGMGR_DCLKCNT_OFST … #define SOCFPGA_FPGMGR_DCLKSTAT_OFST … #define SOCFPGA_FPGMGR_GPIO_INTEN_OFST … #define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST … #define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST … #define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST … #define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST … #define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST … #define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST … #define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST … /* Register bit defines */ /* SOCFPGA_FPGMGR_STAT register mode field values */ #define SOCFPGA_FPGMGR_STAT_POWER_UP … #define SOCFPGA_FPGMGR_STAT_RESET … #define SOCFPGA_FPGMGR_STAT_CFG … #define SOCFPGA_FPGMGR_STAT_INIT … #define SOCFPGA_FPGMGR_STAT_USER_MODE … #define SOCFPGA_FPGMGR_STAT_UNKNOWN … #define SOCFPGA_FPGMGR_STAT_STATE_MASK … /* This is a flag value that doesn't really happen in this register field */ #define SOCFPGA_FPGMGR_STAT_POWER_OFF … #define MSEL_PP16_FAST_NOAES_NODC … #define MSEL_PP16_FAST_AES_NODC … #define MSEL_PP16_FAST_AESOPT_DC … #define MSEL_PP16_SLOW_NOAES_NODC … #define MSEL_PP16_SLOW_AES_NODC … #define MSEL_PP16_SLOW_AESOPT_DC … #define MSEL_PP32_FAST_NOAES_NODC … #define MSEL_PP32_FAST_AES_NODC … #define MSEL_PP32_FAST_AESOPT_DC … #define MSEL_PP32_SLOW_NOAES_NODC … #define MSEL_PP32_SLOW_AES_NODC … #define MSEL_PP32_SLOW_AESOPT_DC … #define SOCFPGA_FPGMGR_STAT_MSEL_MASK … #define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT … /* SOCFPGA_FPGMGR_CTL register */ #define SOCFPGA_FPGMGR_CTL_EN … #define SOCFPGA_FPGMGR_CTL_NCE … #define SOCFPGA_FPGMGR_CTL_NCFGPULL … #define CDRATIO_X1 … #define CDRATIO_X2 … #define CDRATIO_X4 … #define CDRATIO_X8 … #define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK … #define SOCFPGA_FPGMGR_CTL_AXICFGEN … #define CFGWDTH_16 … #define CFGWDTH_32 … #define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK … /* SOCFPGA_FPGMGR_DCLKSTAT register */ #define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE … /* SOCFPGA_FPGMGR_GPIO_* registers share the same bit positions */ #define SOCFPGA_FPGMGR_MON_NSTATUS … #define SOCFPGA_FPGMGR_MON_CONF_DONE … #define SOCFPGA_FPGMGR_MON_INIT_DONE … #define SOCFPGA_FPGMGR_MON_CRC_ERROR … #define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE … #define SOCFPGA_FPGMGR_MON_PR_READY … #define SOCFPGA_FPGMGR_MON_PR_ERROR … #define SOCFPGA_FPGMGR_MON_PR_DONE … #define SOCFPGA_FPGMGR_MON_NCONFIG_PIN … #define SOCFPGA_FPGMGR_MON_NSTATUS_PIN … #define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN … #define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON … #define SOCFPGA_FPGMGR_MON_STATUS_MASK … #define SOCFPGA_FPGMGR_NUM_SUPPLIES … #define SOCFPGA_RESUME_TIMEOUT … /* In power-up order. Reverse for power-down. */ static const char *supply_names[SOCFPGA_FPGMGR_NUM_SUPPLIES] __maybe_unused = …; struct socfpga_fpga_priv { … }; struct cfgmgr_mode { … }; /* For SOCFPGA_FPGMGR_STAT_MSEL field */ static struct cfgmgr_mode cfgmgr_modes[] = …; static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset) { … } static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset, u32 value) { … } static u32 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv, u32 reg_offset) { … } static void socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv, u32 reg_offset, u32 value) { … } static void socfpga_fpga_data_writel(struct socfpga_fpga_priv *priv, u32 value) { … } static inline void socfpga_fpga_set_bitsl(struct socfpga_fpga_priv *priv, u32 offset, u32 bits) { … } static inline void socfpga_fpga_clr_bitsl(struct socfpga_fpga_priv *priv, u32 offset, u32 bits) { … } static u32 socfpga_fpga_mon_status_get(struct socfpga_fpga_priv *priv) { … } static u32 socfpga_fpga_state_get(struct socfpga_fpga_priv *priv) { … } static void socfpga_fpga_clear_done_status(struct socfpga_fpga_priv *priv) { … } /* * Set the DCLKCNT, wait for DCLKSTAT to report the count completed, and clear * the complete status. */ static int socfpga_fpga_dclk_set_and_wait_clear(struct socfpga_fpga_priv *priv, u32 count) { … } static int socfpga_fpga_wait_for_state(struct socfpga_fpga_priv *priv, u32 state) { … } static void socfpga_fpga_enable_irqs(struct socfpga_fpga_priv *priv, u32 irqs) { … } static void socfpga_fpga_disable_irqs(struct socfpga_fpga_priv *priv) { … } static irqreturn_t socfpga_fpga_isr(int irq, void *dev_id) { … } static int socfpga_fpga_wait_for_config_done(struct socfpga_fpga_priv *priv) { … } static int socfpga_fpga_cfg_mode_get(struct socfpga_fpga_priv *priv) { … } static int socfpga_fpga_cfg_mode_set(struct socfpga_fpga_priv *priv) { … } static int socfpga_fpga_reset(struct fpga_manager *mgr) { … } /* * Prepare the FPGA to receive the configuration data. */ static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) { … } /* * Step 9: write data to the FPGA data register */ static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr, const char *buf, size_t count) { … } static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr, struct fpga_image_info *info) { … } /* Translate state register values to FPGA framework state */ static const enum fpga_mgr_states socfpga_state_to_framework_state[] = …; static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr) { … } static const struct fpga_manager_ops socfpga_fpga_ops = …; static int socfpga_fpga_probe(struct platform_device *pdev) { … } #ifdef CONFIG_OF static const struct of_device_id socfpga_fpga_of_match[] = …; MODULE_DEVICE_TABLE(of, socfpga_fpga_of_match); #endif static struct platform_driver socfpga_fpga_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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