// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015 Xilinx Inc. * Copyright (c) 2015, National Instruments Corp. * * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver * in their vendor tree. */ #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/fpga/fpga-mgr.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/mfd/syscon.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/pm.h> #include <linux/regmap.h> #include <linux/string.h> #include <linux/scatterlist.h> /* Offsets into SLCR regmap */ /* FPGA Software Reset Control */ #define SLCR_FPGA_RST_CTRL_OFFSET … /* Level Shifters Enable */ #define SLCR_LVL_SHFTR_EN_OFFSET … /* Constant Definitions */ /* Control Register */ #define CTRL_OFFSET … /* Lock Register */ #define LOCK_OFFSET … /* Interrupt Status Register */ #define INT_STS_OFFSET … /* Interrupt Mask Register */ #define INT_MASK_OFFSET … /* Status Register */ #define STATUS_OFFSET … /* DMA Source Address Register */ #define DMA_SRC_ADDR_OFFSET … /* DMA Destination Address Reg */ #define DMA_DST_ADDR_OFFSET … /* DMA Source Transfer Length */ #define DMA_SRC_LEN_OFFSET … /* DMA Destination Transfer */ #define DMA_DEST_LEN_OFFSET … /* Unlock Register */ #define UNLOCK_OFFSET … /* Misc. Control Register */ #define MCTRL_OFFSET … /* Control Register Bit definitions */ /* Signal to reset FPGA */ #define CTRL_PCFG_PROG_B_MASK … /* Enable PCAP for PR */ #define CTRL_PCAP_PR_MASK … /* Enable PCAP */ #define CTRL_PCAP_MODE_MASK … /* Lower rate to allow decrypt on the fly */ #define CTRL_PCAP_RATE_EN_MASK … /* System booted in secure mode */ #define CTRL_SEC_EN_MASK … /* Miscellaneous Control Register bit definitions */ /* Internal PCAP loopback */ #define MCTRL_PCAP_LPBK_MASK … /* Status register bit definitions */ /* FPGA init status */ #define STATUS_DMA_Q_F … #define STATUS_DMA_Q_E … #define STATUS_PCFG_INIT_MASK … /* Interrupt Status/Mask Register Bit definitions */ /* DMA command done */ #define IXR_DMA_DONE_MASK … /* DMA and PCAP cmd done */ #define IXR_D_P_DONE_MASK … /* FPGA programmed */ #define IXR_PCFG_DONE_MASK … #define IXR_ERROR_FLAGS_MASK … #define IXR_ALL_MASK … /* Miscellaneous constant values */ /* Invalid DMA addr */ #define DMA_INVALID_ADDRESS … /* Used to unlock the dev */ #define UNLOCK_MASK … /* Timeout for polling reset bits */ #define INIT_POLL_TIMEOUT … /* Delay for polling reset bits */ #define INIT_POLL_DELAY … /* Signal this is the last DMA transfer, wait for the AXI and PCAP before * interrupting */ #define DMA_SRC_LAST_TRANSFER … /* Timeout for DMA completion */ #define DMA_TIMEOUT_MS … /* Masks for controlling stuff in SLCR */ /* Disable all Level shifters */ #define LVL_SHFTR_DISABLE_ALL_MASK … /* Enable Level shifters from PS to PL */ #define LVL_SHFTR_ENABLE_PS_TO_PL … /* Enable Level shifters from PL to PS */ #define LVL_SHFTR_ENABLE_PL_TO_PS … /* Enable global resets */ #define FPGA_RST_ALL_MASK … /* Disable global resets */ #define FPGA_RST_NONE_MASK … struct zynq_fpga_priv { … }; static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset, u32 val) { … } static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv, u32 offset) { … } #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) … /* Cause the specified irq mask bits to generate IRQs */ static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable) { … } /* Must be called with dma_lock held */ static void zynq_step_dma(struct zynq_fpga_priv *priv) { … } static irqreturn_t zynq_fpga_isr(int irq, void *data) { … } /* Sanity check the proposed bitstream. It must start with the sync word in * the correct byte order, and be dword aligned. The input is a Xilinx .bin * file with every 32 bit quantity swapped. */ static bool zynq_fpga_has_sync(const u8 *buf, size_t count) { … } static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) { … } static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt) { … } static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info) { … } static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) { … } static const struct fpga_manager_ops zynq_fpga_ops = …; static int zynq_fpga_probe(struct platform_device *pdev) { … } static void zynq_fpga_remove(struct platform_device *pdev) { … } #ifdef CONFIG_OF static const struct of_device_id zynq_fpga_of_match[] = …; MODULE_DEVICE_TABLE(of, zynq_fpga_of_match); #endif static struct platform_driver zynq_fpga_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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