// SPDX-License-Identifier: GPL-2.0 /* * FPGA Manager Driver for Altera Arria10 SoCFPGA * * Copyright (C) 2015-2016 Altera Corporation */ #include <linux/clk.h> #include <linux/device.h> #include <linux/delay.h> #include <linux/fpga/fpga-mgr.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/regmap.h> #define A10_FPGAMGR_DCLKCNT_OFST … #define A10_FPGAMGR_DCLKSTAT_OFST … #define A10_FPGAMGR_IMGCFG_CTL_00_OFST … #define A10_FPGAMGR_IMGCFG_CTL_01_OFST … #define A10_FPGAMGR_IMGCFG_CTL_02_OFST … #define A10_FPGAMGR_IMGCFG_STAT_OFST … #define A10_FPGAMGR_DCLKSTAT_DCLKDONE … #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG … #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS … #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE … #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG … #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE … #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE … #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG … #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST … #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE … #define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL … #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK … #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT … #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH … #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT … #define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR … #define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE … #define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE … #define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN … #define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN … #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY … #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE … #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR … #define A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN … #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK … #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT … /* FPGA CD Ratio Value */ #define CDRATIO_x1 … #define CDRATIO_x2 … #define CDRATIO_x4 … #define CDRATIO_x8 … /* Configuration width 16/32 bit */ #define CFGWDTH_32 … #define CFGWDTH_16 … /* * struct a10_fpga_priv - private data for fpga manager * @regmap: regmap for register access * @fpga_data_addr: iomap for single address data register to FPGA * @clk: clock */ struct a10_fpga_priv { … }; static bool socfpga_a10_fpga_writeable_reg(struct device *dev, unsigned int reg) { … } static bool socfpga_a10_fpga_readable_reg(struct device *dev, unsigned int reg) { … } static const struct regmap_config socfpga_a10_fpga_regmap_config = …; /* * from the register map description of cdratio in imgcfg_ctrl_02: * Normal Configuration : 32bit Passive Parallel * Partial Reconfiguration : 16bit Passive Parallel */ static void socfpga_a10_fpga_set_cfg_width(struct a10_fpga_priv *priv, int width) { … } static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv, u32 count) { … } #define RBF_ENCRYPTION_MODE_OFFSET … #define RBF_DECOMPRESS_OFFSET … static int socfpga_a10_fpga_encrypted(u32 *buf32, size_t buf32_size) { … } static int socfpga_a10_fpga_compressed(u32 *buf32, size_t buf32_size) { … } static unsigned int socfpga_a10_fpga_get_cd_ratio(unsigned int cfg_width, bool encrypt, bool compress) { … } static int socfpga_a10_fpga_set_cdratio(struct fpga_manager *mgr, unsigned int cfg_width, const char *buf, size_t count) { … } static u32 socfpga_a10_fpga_read_stat(struct a10_fpga_priv *priv) { … } static int socfpga_a10_fpga_wait_for_pr_ready(struct a10_fpga_priv *priv) { … } static int socfpga_a10_fpga_wait_for_pr_done(struct a10_fpga_priv *priv) { … } /* Start the FPGA programming by initialize the FPGA Manager */ static int socfpga_a10_fpga_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) { … } /* * write data to the FPGA data register */ static int socfpga_a10_fpga_write(struct fpga_manager *mgr, const char *buf, size_t count) { … } static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info) { … } static enum fpga_mgr_states socfpga_a10_fpga_state(struct fpga_manager *mgr) { … } static const struct fpga_manager_ops socfpga_a10_fpga_mgr_ops = …; static int socfpga_a10_fpga_probe(struct platform_device *pdev) { … } static void socfpga_a10_fpga_remove(struct platform_device *pdev) { … } static const struct of_device_id socfpga_a10_fpga_of_match[] = …; MODULE_DEVICE_TABLE(of, socfpga_a10_fpga_of_match); static struct platform_driver socfpga_a10_fpga_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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