/* SPDX-License-Identifier: GPL-2.0 */ /* * Driver Header File for FPGA Device Feature List (DFL) Support * * Copyright (C) 2017-2018 Intel Corporation, Inc. * * Authors: * Kang Luwei <[email protected]> * Zhang Yi <[email protected]> * Wu Hao <[email protected]> * Xiao Guangrong <[email protected]> */ #ifndef __FPGA_DFL_H #define __FPGA_DFL_H #include <linux/bitfield.h> #include <linux/cdev.h> #include <linux/delay.h> #include <linux/eventfd.h> #include <linux/fs.h> #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/uuid.h> #include <linux/fpga/fpga-region.h> /* maximum supported number of ports */ #define MAX_DFL_FPGA_PORT_NUM … /* plus one for fme device */ #define MAX_DFL_FEATURE_DEV_NUM … /* Reserved 0xfe for Header Group Register and 0xff for AFU */ #define FEATURE_ID_FIU_HEADER … #define FEATURE_ID_AFU … #define FME_FEATURE_ID_HEADER … #define FME_FEATURE_ID_THERMAL_MGMT … #define FME_FEATURE_ID_POWER_MGMT … #define FME_FEATURE_ID_GLOBAL_IPERF … #define FME_FEATURE_ID_GLOBAL_ERR … #define FME_FEATURE_ID_PR_MGMT … #define FME_FEATURE_ID_HSSI … #define FME_FEATURE_ID_GLOBAL_DPERF … #define PORT_FEATURE_ID_HEADER … #define PORT_FEATURE_ID_AFU … #define PORT_FEATURE_ID_ERROR … #define PORT_FEATURE_ID_UMSG … #define PORT_FEATURE_ID_UINT … #define PORT_FEATURE_ID_STP … /* * Device Feature Header Register Set * * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. * For AFUs, they have DFH + GUID as common header registers. * For private features, they only have DFH register as common header. */ #define DFH … #define GUID_L … #define GUID_H … #define NEXT_AFU … #define DFH_SIZE … /* Device Feature Header Register Bitfield */ #define DFH_ID … #define DFH_ID_FIU_FME … #define DFH_ID_FIU_PORT … #define DFH_REVISION … #define DFH_NEXT_HDR_OFST … #define DFH_EOL … #define DFH_VERSION … #define DFH_TYPE … #define DFH_TYPE_AFU … #define DFH_TYPE_PRIVATE … #define DFH_TYPE_FIU … /* * DFHv1 Register Offset definitons * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA * as common header registers */ #define DFHv1_CSR_ADDR … #define DFHv1_CSR_SIZE_GRP … #define DFHv1_PARAM_HDR … /* * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start), * 1'b1 = absolute (ARM or other non-PCIe use) */ #define DFHv1_CSR_ADDR_REL … /* CSR Header Register Bit Definitions */ #define DFHv1_CSR_ADDR_MASK … /* CSR SIZE Goup Register Bit Definitions */ #define DFHv1_CSR_SIZE_GRP_INSTANCE_ID … #define DFHv1_CSR_SIZE_GRP_GROUPING_ID … #define DFHv1_CSR_SIZE_GRP_HAS_PARAMS … #define DFHv1_CSR_SIZE_GRP_SIZE … /* PARAM Header Register Bit Definitions */ #define DFHv1_PARAM_HDR_ID … #define DFHv1_PARAM_HDR_VER … #define DFHv1_PARAM_HDR_NEXT_OFFSET … #define DFHv1_PARAM_HDR_NEXT_EOP … #define DFHv1_PARAM_DATA … #define DFHv1_PARAM_ID_MSI_X … #define DFHv1_PARAM_MSI_X_NUMV … #define DFHv1_PARAM_MSI_X_STARTV … /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST … /* FME Header Register Set */ #define FME_HDR_DFH … #define FME_HDR_GUID_L … #define FME_HDR_GUID_H … #define FME_HDR_NEXT_AFU … #define FME_HDR_CAP … #define FME_HDR_PORT_OFST(n) … #define FME_PORT_OFST_BAR_SKIP … #define FME_HDR_BITSTREAM_ID … #define FME_HDR_BITSTREAM_MD … /* FME Fab Capability Register Bitfield */ #define FME_CAP_FABRIC_VERID … #define FME_CAP_SOCKET_ID … #define FME_CAP_PCIE0_LINK_AVL … #define FME_CAP_PCIE1_LINK_AVL … #define FME_CAP_COHR_LINK_AVL … #define FME_CAP_IOMMU_AVL … #define FME_CAP_NUM_PORTS … #define FME_CAP_ADDR_WIDTH … #define FME_CAP_CACHE_SIZE … #define FME_CAP_CACHE_ASSOC … /* FME Port Offset Register Bitfield */ /* Offset to port device feature header */ #define FME_PORT_OFST_DFH_OFST … /* PCI Bar ID for this port */ #define FME_PORT_OFST_BAR_ID … /* AFU MMIO access permission. 1 - VF, 0 - PF. */ #define FME_PORT_OFST_ACC_CTRL … #define FME_PORT_OFST_ACC_PF … #define FME_PORT_OFST_ACC_VF … #define FME_PORT_OFST_IMP … /* FME Error Capability Register */ #define FME_ERROR_CAP … /* FME Error Capability Register Bitfield */ #define FME_ERROR_CAP_SUPP_INT … #define FME_ERROR_CAP_INT_VECT … /* PORT Header Register Set */ #define PORT_HDR_DFH … #define PORT_HDR_GUID_L … #define PORT_HDR_GUID_H … #define PORT_HDR_NEXT_AFU … #define PORT_HDR_CAP … #define PORT_HDR_CTRL … #define PORT_HDR_STS … #define PORT_HDR_USRCLK_CMD0 … #define PORT_HDR_USRCLK_CMD1 … #define PORT_HDR_USRCLK_STS0 … #define PORT_HDR_USRCLK_STS1 … /* Port Capability Register Bitfield */ #define PORT_CAP_PORT_NUM … #define PORT_CAP_MMIO_SIZE … #define PORT_CAP_SUPP_INT_NUM … /* Port Control Register Bitfield */ #define PORT_CTRL_SFTRST … /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ #define PORT_CTRL_LATENCY … #define PORT_CTRL_SFTRST_ACK … /* Port Status Register Bitfield */ #define PORT_STS_AP2_EVT … #define PORT_STS_AP1_EVT … #define PORT_STS_PWR_STATE … #define PORT_STS_PWR_STATE_NORM … #define PORT_STS_PWR_STATE_AP1 … #define PORT_STS_PWR_STATE_AP2 … #define PORT_STS_PWR_STATE_AP6 … /* Port Error Capability Register */ #define PORT_ERROR_CAP … /* Port Error Capability Register Bitfield */ #define PORT_ERROR_CAP_SUPP_INT … #define PORT_ERROR_CAP_INT_VECT … /* Port Uint Capability Register */ #define PORT_UINT_CAP … /* Port Uint Capability Register Bitfield */ #define PORT_UINT_CAP_INT_NUM … #define PORT_UINT_CAP_FST_VECT … /** * struct dfl_fpga_port_ops - port ops * * @name: name of this port ops, to match with port platform device. * @owner: pointer to the module which owns this port ops. * @node: node to link port ops to global list. * @get_id: get port id from hardware. * @enable_set: enable/disable the port. */ struct dfl_fpga_port_ops { … }; void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops); void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops); struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev); void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops); int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id); /** * struct dfl_feature_id - dfl private feature id * * @id: unique dfl private feature id. */ struct dfl_feature_id { … }; /** * struct dfl_feature_driver - dfl private feature driver * * @id_table: id_table for dfl private features supported by this driver. * @ops: ops of this dfl private feature driver. */ struct dfl_feature_driver { … }; /** * struct dfl_feature_irq_ctx - dfl private feature interrupt context * * @irq: Linux IRQ number of this interrupt. * @trigger: eventfd context to signal when interrupt happens. * @name: irq name needed when requesting irq. */ struct dfl_feature_irq_ctx { … }; /** * struct dfl_feature - sub feature of the feature devices * * @dev: ptr to pdev of the feature device which has the sub feature. * @id: sub feature id. * @revision: revision of this sub feature. * @resource_index: each sub feature has one mmio resource for its registers. * this index is used to find its mmio resource from the * feature dev (platform device)'s resources. * @ioaddr: mapped mmio resource address. * @irq_ctx: interrupt context list. * @nr_irqs: number of interrupt contexts. * @ops: ops of this sub feature. * @ddev: ptr to the dfl device of this sub feature. * @priv: priv data of this feature. * @dfh_version: version of the DFH * @param_size: size of dfh parameters * @params: point to memory copy of dfh parameters */ struct dfl_feature { … }; #define FEATURE_DEV_ID_UNUSED … /** * struct dfl_feature_platform_data - platform data for feature devices * * @node: node to link feature devs to container device's port_dev_list. * @lock: mutex to protect platform data. * @cdev: cdev of feature dev. * @dev: ptr to platform device linked with this platform data. * @dfl_cdev: ptr to container device. * @id: id used for this feature device. * @disable_count: count for port disable. * @excl_open: set on feature device exclusive open. * @open_count: count for feature device open. * @num: number for sub features. * @private: ptr to feature dev private data. * @features: sub features of this feature dev. */ struct dfl_feature_platform_data { … }; static inline int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, bool excl) { … } static inline void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) { … } static inline int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) { … } static inline void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata, void *private) { … } static inline void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata) { … } struct dfl_feature_ops { … }; #define DFL_FPGA_FEATURE_DEV_FME … #define DFL_FPGA_FEATURE_DEV_PORT … void dfl_fpga_dev_feature_uinit(struct platform_device *pdev); int dfl_fpga_dev_feature_init(struct platform_device *pdev, struct dfl_feature_driver *feature_drvs); int dfl_fpga_dev_ops_register(struct platform_device *pdev, const struct file_operations *fops, struct module *owner); void dfl_fpga_dev_ops_unregister(struct platform_device *pdev); static inline struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode) { … } #define dfl_fpga_dev_for_each_feature(pdata, feature) … static inline struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id) { … } static inline void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id) { … } static inline struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata) { … } static inline bool dfl_feature_is_fme(void __iomem *base) { … } static inline bool dfl_feature_is_port(void __iomem *base) { … } static inline u8 dfl_feature_revision(void __iomem *base) { … } /** * struct dfl_fpga_enum_info - DFL FPGA enumeration information * * @dev: parent device. * @dfls: list of device feature lists. * @nr_irqs: number of irqs for all feature devices. * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers. */ struct dfl_fpga_enum_info { … }; /** * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info * * @start: base address of this device feature list. * @len: size of this device feature list. * @node: node in list of device feature lists. */ struct dfl_fpga_enum_dfl { … }; struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev); int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info, resource_size_t start, resource_size_t len); int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info, unsigned int nr_irqs, int *irq_table); void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); /** * struct dfl_fpga_cdev - container device of DFL based FPGA * * @parent: parent device of this container device. * @region: base fpga region. * @fme_dev: FME feature device under this container device. * @lock: mutex lock to protect the port device list. * @port_dev_list: list of all port feature devices under this container device. * @released_port_num: released port number under this container device. */ struct dfl_fpga_cdev { … }; struct dfl_fpga_cdev * dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info); void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev); /* * need to drop the device reference with put_device() after use port platform * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port * functions. */ struct platform_device * __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, int (*match)(struct platform_device *, void *)); static inline struct platform_device * dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, int (*match)(struct platform_device *, void *)) { … } int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id); int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id); void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev); int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf); int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start, unsigned int count, int32_t *fds); long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev, struct dfl_feature *feature, unsigned long arg); long dfl_feature_ioctl_set_irq(struct platform_device *pdev, struct dfl_feature *feature, unsigned long arg); #endif /* __FPGA_DFL_H */
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