// SPDX-License-Identifier: GPL-2.0 /* * FPGA Manager Driver for FPGA Management Engine (FME) * * Copyright (C) 2017-2018 Intel Corporation, Inc. * * Authors: * Kang Luwei <[email protected]> * Xiao Guangrong <[email protected]> * Wu Hao <[email protected]> * Joseph Grecco <[email protected]> * Enno Luebbers <[email protected]> * Tim Whisonant <[email protected]> * Ananda Ravuri <[email protected]> * Christopher Rauer <[email protected]> * Henry Mitchel <[email protected]> */ #include <linux/bitfield.h> #include <linux/module.h> #include <linux/iopoll.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/fpga/fpga-mgr.h> #include "dfl-fme-pr.h" /* FME Partial Reconfiguration Sub Feature Register Set */ #define FME_PR_DFH … #define FME_PR_CTRL … #define FME_PR_STS … #define FME_PR_DATA … #define FME_PR_ERR … #define FME_PR_INTFC_ID_L … #define FME_PR_INTFC_ID_H … /* FME PR Control Register Bitfield */ #define FME_PR_CTRL_PR_RST … #define FME_PR_CTRL_PR_RSTACK … #define FME_PR_CTRL_PR_RGN_ID … #define FME_PR_CTRL_PR_START … #define FME_PR_CTRL_PR_COMPLETE … /* FME PR Status Register Bitfield */ /* Number of available entries in HW queue inside the PR engine. */ #define FME_PR_STS_PR_CREDIT … #define FME_PR_STS_PR_STS … #define FME_PR_STS_PR_STS_IDLE … #define FME_PR_STS_PR_CTRLR_STS … #define FME_PR_STS_PR_HOST_STS … /* FME PR Data Register Bitfield */ /* PR data from the raw-binary file. */ #define FME_PR_DATA_PR_DATA_RAW … /* FME PR Error Register */ /* PR Operation errors detected. */ #define FME_PR_ERR_OPERATION_ERR … /* CRC error detected. */ #define FME_PR_ERR_CRC_ERR … /* Incompatible PR bitstream detected. */ #define FME_PR_ERR_INCOMPATIBLE_BS … /* PR data push protocol violated. */ #define FME_PR_ERR_PROTOCOL_ERR … /* PR data fifo overflow error detected */ #define FME_PR_ERR_FIFO_OVERFLOW … #define PR_WAIT_TIMEOUT … #define PR_HOST_STATUS_IDLE … struct fme_mgr_priv { … }; static u64 pr_error_to_mgr_status(u64 err) { … } static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr) { … } static int fme_mgr_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) { … } static int fme_mgr_write(struct fpga_manager *mgr, const char *buf, size_t count) { … } static int fme_mgr_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info) { … } static u64 fme_mgr_status(struct fpga_manager *mgr) { … } static const struct fpga_manager_ops fme_mgr_ops = …; static void fme_mgr_get_compat_id(void __iomem *fme_pr, struct fpga_compat_id *id) { … } static int fme_mgr_probe(struct platform_device *pdev) { … } static struct platform_driver fme_mgr_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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