// SPDX-License-Identifier: GPL-2.0 /* * Driver for FPGA Device Feature List (DFL) Support * * Copyright (C) 2017-2018 Intel Corporation, Inc. * * Authors: * Kang Luwei <[email protected]> * Zhang Yi <[email protected]> * Wu Hao <[email protected]> * Xiao Guangrong <[email protected]> */ #include <linux/dfl.h> #include <linux/fpga-dfl.h> #include <linux/module.h> #include <linux/overflow.h> #include <linux/uaccess.h> #include "dfl.h" static DEFINE_MUTEX(dfl_id_mutex); /* * when adding a new feature dev support in DFL framework, it's required to * add a new item in enum dfl_id_type and provide related information in below * dfl_devs table which is indexed by dfl_id_type, e.g. name string used for * platform device creation (define name strings in dfl.h, as they could be * reused by platform device drivers). * * if the new feature dev needs chardev support, then it's required to add * a new item in dfl_chardevs table and configure dfl_devs[i].devt_type as * index to dfl_chardevs table. If no chardev support just set devt_type * as one invalid index (DFL_FPGA_DEVT_MAX). */ enum dfl_fpga_devt_type { … }; static struct lock_class_key dfl_pdata_keys[DFL_ID_MAX]; static const char *dfl_pdata_key_strings[DFL_ID_MAX] = …; /** * struct dfl_dev_info - dfl feature device information. * @name: name string of the feature platform device. * @dfh_id: id value in Device Feature Header (DFH) register by DFL spec. * @id: idr id of the feature dev. * @devt_type: index to dfl_chrdevs[]. */ struct dfl_dev_info { … }; /* it is indexed by dfl_id_type */ static struct dfl_dev_info dfl_devs[] = …; /** * struct dfl_chardev_info - chardev information of dfl feature device * @name: nmae string of the char device. * @devt: devt of the char device. */ struct dfl_chardev_info { … }; /* indexed by enum dfl_fpga_devt_type */ static struct dfl_chardev_info dfl_chrdevs[] = …; static void dfl_ids_init(void) { … } static void dfl_ids_destroy(void) { … } static int dfl_id_alloc(enum dfl_id_type type, struct device *dev) { … } static void dfl_id_free(enum dfl_id_type type, int id) { … } static enum dfl_id_type feature_dev_id_type(struct platform_device *pdev) { … } static enum dfl_id_type dfh_id_to_type(u16 id) { … } /* * introduce a global port_ops list, it allows port drivers to register ops * in such list, then other feature devices (e.g. FME), could use the port * functions even related port platform device is hidden. Below is one example, * in virtualization case of PCIe-based FPGA DFL device, when SRIOV is * enabled, port (and it's AFU) is turned into VF and port platform device * is hidden from system but it's still required to access port to finish FPGA * reconfiguration function in FME. */ static DEFINE_MUTEX(dfl_port_ops_mutex); static LIST_HEAD(dfl_port_ops_list); /** * dfl_fpga_port_ops_get - get matched port ops from the global list * @pdev: platform device to match with associated port ops. * Return: matched port ops on success, NULL otherwise. * * Please note that must dfl_fpga_port_ops_put after use the port_ops. */ struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_port_ops_put - put port ops * @ops: port ops. */ void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_port_ops_add - add port_ops to global list * @ops: port ops to add. */ void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_port_ops_del - remove port_ops from global list * @ops: port ops to del. */ void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_check_port_id - check the port id * @pdev: port platform device. * @pport_id: port id to compare. * * Return: 1 if port device matches with given port id, otherwise 0. */ int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id) { … } EXPORT_SYMBOL_GPL(…); static DEFINE_IDA(dfl_device_ida); static const struct dfl_device_id * dfl_match_one_device(const struct dfl_device_id *id, struct dfl_device *ddev) { … } static int dfl_bus_match(struct device *dev, const struct device_driver *drv) { … } static int dfl_bus_probe(struct device *dev) { … } static void dfl_bus_remove(struct device *dev) { … } static int dfl_bus_uevent(const struct device *dev, struct kobj_uevent_env *env) { … } static ssize_t type_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RO(type); static ssize_t feature_id_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RO(feature_id); static struct attribute *dfl_dev_attrs[] = …; ATTRIBUTE_GROUPS(…); static const struct bus_type dfl_bus_type = …; static void release_dfl_dev(struct device *dev) { … } static struct dfl_device * dfl_dev_add(struct dfl_feature_platform_data *pdata, struct dfl_feature *feature) { … } static void dfl_devs_remove(struct dfl_feature_platform_data *pdata) { … } static int dfl_devs_add(struct dfl_feature_platform_data *pdata) { … } int __dfl_driver_register(struct dfl_driver *dfl_drv, struct module *owner) { … } EXPORT_SYMBOL(…); void dfl_driver_unregister(struct dfl_driver *dfl_drv) { … } EXPORT_SYMBOL(…); #define is_header_feature(feature) … /** * dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device * @pdev: feature device. */ void dfl_fpga_dev_feature_uinit(struct platform_device *pdev) { … } EXPORT_SYMBOL_GPL(…); static int dfl_feature_instance_init(struct platform_device *pdev, struct dfl_feature_platform_data *pdata, struct dfl_feature *feature, struct dfl_feature_driver *drv) { … } static bool dfl_feature_drv_match(struct dfl_feature *feature, struct dfl_feature_driver *driver) { … } /** * dfl_fpga_dev_feature_init - init for sub features of dfl feature device * @pdev: feature device. * @feature_drvs: drvs for sub features. * * This function will match sub features with given feature drvs list and * use matched drv to init related sub feature. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_dev_feature_init(struct platform_device *pdev, struct dfl_feature_driver *feature_drvs) { … } EXPORT_SYMBOL_GPL(…); static void dfl_chardev_uinit(void) { … } static int dfl_chardev_init(void) { … } static dev_t dfl_get_devt(enum dfl_fpga_devt_type type, int id) { … } /** * dfl_fpga_dev_ops_register - register cdev ops for feature dev * * @pdev: feature dev. * @fops: file operations for feature dev's cdev. * @owner: owning module/driver. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_dev_ops_register(struct platform_device *pdev, const struct file_operations *fops, struct module *owner) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_dev_ops_unregister - unregister cdev ops for feature dev * @pdev: feature dev. */ void dfl_fpga_dev_ops_unregister(struct platform_device *pdev) { … } EXPORT_SYMBOL_GPL(…); /** * struct build_feature_devs_info - info collected during feature dev build. * * @dev: device to enumerate. * @cdev: the container device for all feature devices. * @nr_irqs: number of irqs for all feature devices. * @irq_table: Linux IRQ numbers for all irqs, indexed by local irq index of * this device. * @feature_dev: current feature device. * @ioaddr: header register region address of current FIU in enumeration. * @start: register resource start of current FIU. * @len: max register resource length of current FIU. * @sub_features: a sub features linked list for feature device in enumeration. * @feature_num: number of sub features for feature device in enumeration. */ struct build_feature_devs_info { … }; /** * struct dfl_feature_info - sub feature info collected during feature dev build * * @fid: id of this sub feature. * @revision: revision of this sub feature * @dfh_version: version of Device Feature Header (DFH) * @mmio_res: mmio resource of this sub feature. * @ioaddr: mapped base address of mmio resource. * @node: node in sub_features linked list. * @irq_base: start of irq index in this sub feature. * @nr_irqs: number of irqs of this sub feature. * @param_size: size DFH parameters. * @params: DFH parameter data. */ struct dfl_feature_info { … }; static void dfl_fpga_cdev_add_port_dev(struct dfl_fpga_cdev *cdev, struct platform_device *port) { … } /* * register current feature device, it is called when we need to switch to * another feature parsing or we have parsed all features on given device * feature list. */ static int build_info_commit_dev(struct build_feature_devs_info *binfo) { … } static int build_info_create_dev(struct build_feature_devs_info *binfo, enum dfl_id_type type) { … } static void build_info_free(struct build_feature_devs_info *binfo) { … } static inline u32 feature_size(u64 value) { … } static u16 feature_id(u64 value) { … } static u64 *find_param(u64 *params, resource_size_t max, int param_id) { … } /** * dfh_find_param() - find parameter block for the given parameter id * @dfl_dev: dfl device * @param_id: id of dfl parameter * @psize: destination to store size of parameter data in bytes * * Return: pointer to start of parameter data, PTR_ERR otherwise. */ void *dfh_find_param(struct dfl_device *dfl_dev, int param_id, size_t *psize) { … } EXPORT_SYMBOL_GPL(…); static int parse_feature_irqs(struct build_feature_devs_info *binfo, resource_size_t ofst, struct dfl_feature_info *finfo) { … } static int dfh_get_param_size(void __iomem *dfh_base, resource_size_t max) { … } /* * when create sub feature instances, for private features, it doesn't need * to provide resource size and feature id as they could be read from DFH * register. For afu sub feature, its register region only contains user * defined registers, so never trust any information from it, just use the * resource size information provided by its parent FIU. */ static int create_feature_instance(struct build_feature_devs_info *binfo, resource_size_t ofst, resource_size_t size, u16 fid) { … } static int parse_feature_port_afu(struct build_feature_devs_info *binfo, resource_size_t ofst) { … } #define is_feature_dev_detected(binfo) … static int parse_feature_afu(struct build_feature_devs_info *binfo, resource_size_t ofst) { … } static int build_info_prepare(struct build_feature_devs_info *binfo, resource_size_t start, resource_size_t len) { … } static void build_info_complete(struct build_feature_devs_info *binfo) { … } static int parse_feature_fiu(struct build_feature_devs_info *binfo, resource_size_t ofst) { … } static int parse_feature_private(struct build_feature_devs_info *binfo, resource_size_t ofst) { … } /** * parse_feature - parse a feature on given device feature list * * @binfo: build feature devices information. * @ofst: offset to current FIU header */ static int parse_feature(struct build_feature_devs_info *binfo, resource_size_t ofst) { … } static int parse_feature_list(struct build_feature_devs_info *binfo, resource_size_t start, resource_size_t len) { … } struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev) { … } EXPORT_SYMBOL_GPL(…); void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_enum_info_add_dfl - add info of a device feature list to enum info * * @info: ptr to dfl_fpga_enum_info * @start: mmio resource address of the device feature list. * @len: mmio resource length of the device feature list. * * One FPGA device may have one or more Device Feature Lists (DFLs), use this * function to add information of each DFL to common data structure for next * step enumeration. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info, resource_size_t start, resource_size_t len) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_enum_info_add_irq - add irq table to enum info * * @info: ptr to dfl_fpga_enum_info * @nr_irqs: number of irqs of the DFL fpga device to be enumerated. * @irq_table: Linux IRQ numbers for all irqs, indexed by local irq index of * this device. * * One FPGA device may have several interrupts. This function adds irq * information of the DFL fpga device to enum info for next step enumeration. * This function should be called before dfl_fpga_feature_devs_enumerate(). * As we only support one irq domain for all DFLs in the same enum info, adding * irq table a second time for the same enum info will return error. * * If we need to enumerate DFLs which belong to different irq domains, we * should fill more enum info and enumerate them one by one. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info, unsigned int nr_irqs, int *irq_table) { … } EXPORT_SYMBOL_GPL(…); static int remove_feature_dev(struct device *dev, void *data) { … } static void remove_feature_devs(struct dfl_fpga_cdev *cdev) { … } /** * dfl_fpga_feature_devs_enumerate - enumerate feature devices * @info: information for enumeration. * * This function creates a container device (base FPGA region), enumerates * feature devices based on the enumeration info and creates platform devices * under the container device. * * Return: dfl_fpga_cdev struct on success, -errno on failure */ struct dfl_fpga_cdev * dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_feature_devs_remove - remove all feature devices * @cdev: fpga container device. * * Remove the container device and all feature devices under given container * devices. */ void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev) { … } EXPORT_SYMBOL_GPL(…); /** * __dfl_fpga_cdev_find_port - find a port under given container device * * @cdev: container device * @data: data passed to match function * @match: match function used to find specific port from the port device list * * Find a port device under container device. This function needs to be * invoked with lock held. * * Return: pointer to port's platform device if successful, NULL otherwise. * * NOTE: you will need to drop the device reference with put_device() after use. */ struct platform_device * __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, int (*match)(struct platform_device *, void *)) { … } EXPORT_SYMBOL_GPL(…); static int __init dfl_fpga_init(void) { … } /** * dfl_fpga_cdev_release_port - release a port platform device * * @cdev: parent container device. * @port_id: id of the port platform device. * * This function allows user to release a port platform device. This is a * mandatory step before turn a port from PF into VF for SRIOV support. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_cdev_assign_port - assign a port platform device back * * @cdev: parent container device. * @port_id: id of the port platform device. * * This function allows user to assign a port platform device back. This is * a mandatory step after disable SRIOV support. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) { … } EXPORT_SYMBOL_GPL(…); static void config_port_access_mode(struct device *fme_dev, int port_id, bool is_vf) { … } #define config_port_vf_mode(dev, id) … #define config_port_pf_mode(dev, id) … /** * dfl_fpga_cdev_config_ports_pf - configure ports to PF access mode * * @cdev: parent container device. * * This function is needed in sriov configuration routine. It could be used to * configure the all released ports from VF access mode to PF. */ void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_fpga_cdev_config_ports_vf - configure ports to VF access mode * * @cdev: parent container device. * @num_vfs: VF device number. * * This function is needed in sriov configuration routine. It could be used to * configure the released ports from PF access mode to VF. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs) { … } EXPORT_SYMBOL_GPL(…); static irqreturn_t dfl_irq_handler(int irq, void *arg) { … } static int do_set_irq_trigger(struct dfl_feature *feature, unsigned int idx, int fd) { … } /** * dfl_fpga_set_irq_triggers - set eventfd triggers for dfl feature interrupts * * @feature: dfl sub feature. * @start: start of irq index in this dfl sub feature. * @count: number of irqs. * @fds: eventfds to bind with irqs. unbind related irq if fds[n] is negative. * unbind "count" specified number of irqs if fds ptr is NULL. * * Bind given eventfds with irqs in this dfl sub feature. Unbind related irq if * fds[n] is negative. Unbind "count" specified number of irqs if fds ptr is * NULL. * * Return: 0 on success, negative error code otherwise. */ int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start, unsigned int count, int32_t *fds) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_feature_ioctl_get_num_irqs - dfl feature _GET_IRQ_NUM ioctl interface. * @pdev: the feature device which has the sub feature * @feature: the dfl sub feature * @arg: ioctl argument * * Return: 0 on success, negative error code otherwise. */ long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev, struct dfl_feature *feature, unsigned long arg) { … } EXPORT_SYMBOL_GPL(…); /** * dfl_feature_ioctl_set_irq - dfl feature _SET_IRQ ioctl interface. * @pdev: the feature device which has the sub feature * @feature: the dfl sub feature * @arg: ioctl argument * * Return: 0 on success, negative error code otherwise. */ long dfl_feature_ioctl_set_irq(struct platform_device *pdev, struct dfl_feature *feature, unsigned long arg) { … } EXPORT_SYMBOL_GPL(…); static void __exit dfl_fpga_exit(void) { … } module_init(…) …; module_exit(dfl_fpga_exit); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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