/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CF_FSI_FW_H #define __CF_FSI_FW_H /* * uCode file layout * * 0000...03ff : m68k exception vectors * 0400...04ff : Header info & boot config block * 0500....... : Code & stack */ /* * Header info & boot config area * * The Header info is built into the ucode and provide version and * platform information. * * the Boot config needs to be adjusted by the ARM prior to starting * the ucode if the Command/Status area isn't at 0x320000 in CF space * (ie. beginning of SRAM). */ #define HDR_OFFSET … /* Info: Signature & version */ #define HDR_SYS_SIG … #define SYS_SIG_SHARED … #define SYS_SIG_SPLIT … #define HDR_FW_VERS … #define HDR_API_VERS … #define API_VERSION_MAJ … #define API_VERSION_MIN … #define HDR_FW_OPTIONS … #define FW_OPTION_TRACE_EN … #define FW_OPTION_CONT_CLOCK … #define HDR_FW_SIZE … /* Boot Config: Address of Command/Status area */ #define HDR_CMD_STAT_AREA … #define HDR_FW_CONTROL … #define FW_CONTROL_CONT_CLOCK … #define FW_CONTROL_DUMMY_RD … #define FW_CONTROL_USE_STOP … #define HDR_CLOCK_GPIO_VADDR … #define HDR_CLOCK_GPIO_DADDR … #define HDR_DATA_GPIO_VADDR … #define HDR_DATA_GPIO_DADDR … #define HDR_TRANS_GPIO_VADDR … #define HDR_TRANS_GPIO_DADDR … #define HDR_CLOCK_GPIO_BIT … #define HDR_DATA_GPIO_BIT … #define HDR_TRANS_GPIO_BIT … /* * Command/Status area layout: Main part */ /* Command/Status register: * * +---------------------------+ * | STAT | RLEN | CLEN | CMD | * | 8 | 8 | 8 | 8 | * +---------------------------+ * | | | | * status | | | * Response len | | * (in bits) | | * | | * Command len | * (in bits) | * | * Command code * * Due to the big endian layout, that means that a byte read will * return the status byte */ #define CMD_STAT_REG … #define CMD_REG_CMD_MASK … #define CMD_REG_CMD_SHIFT … #define CMD_NONE … #define CMD_COMMAND … #define CMD_BREAK … #define CMD_IDLE_CLOCKS … #define CMD_INVALID … #define CMD_REG_CLEN_MASK … #define CMD_REG_CLEN_SHIFT … #define CMD_REG_RLEN_MASK … #define CMD_REG_RLEN_SHIFT … #define CMD_REG_STAT_MASK … #define CMD_REG_STAT_SHIFT … #define STAT_WORKING … #define STAT_COMPLETE … #define STAT_ERR_INVAL_CMD … #define STAT_ERR_INVAL_IRQ … #define STAT_ERR_MTOE … /* Response tag & CRC */ #define STAT_RTAG … /* Response CRC */ #define STAT_RCRC … /* Echo and Send delay */ #define ECHO_DLY_REG … #define SEND_DLY_REG … /* Command data area * * Last byte of message must be left aligned */ #define CMD_DATA … /* Response data area, right aligned, unused top bits are 1 */ #define RSP_DATA … /* Misc */ #define INT_CNT … #define BAD_INT_VEC … #define CF_STARTED … #define CLK_CNT … /* * SRAM layout: GPIO arbitration part */ #define ARB_REG … #define ARB_ARM_REQ … #define ARB_ARM_ACK … /* Misc2 */ #define CF_RESET_D0 … #define CF_RESET_D1 … #define BAD_INT_S0 … #define BAD_INT_S1 … #define STOP_CNT … /* Internal */ /* * SRAM layout: Trace buffer (debug builds only) */ #define TRACEBUF … #define TR_CLKOBIT0 … #define TR_CLKOBIT1 … #define TR_CLKOSTART … #define TR_OLEN … #define TR_CLKZ … #define TR_CLKWSTART … #define TR_CLKTAG … #define TR_CLKDATA … #define TR_CLKCRC … #define TR_CLKIBIT0 … #define TR_CLKIBIT1 … #define TR_END … #endif /* __CF_FSI_FW_H */
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