/* SPDX-License-Identifier: GPL-2.0 */ /* * Interconnect framework driver for i.MX SoC * * Copyright (c) 2019, BayLibre * Copyright (c) 2019-2020, NXP * Author: Alexandre Bailon <[email protected]> */ #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H #define __DT_BINDINGS_INTERCONNECT_IMX8MM_H #define IMX8MM_ICN_NOC … #define IMX8MM_ICS_DRAM … #define IMX8MM_ICS_OCRAM … #define IMX8MM_ICM_A53 … #define IMX8MM_ICM_VPU_H1 … #define IMX8MM_ICM_VPU_G1 … #define IMX8MM_ICM_VPU_G2 … #define IMX8MM_ICN_VIDEO … #define IMX8MM_ICM_GPU2D … #define IMX8MM_ICM_GPU3D … #define IMX8MM_ICN_GPU … #define IMX8MM_ICM_CSI … #define IMX8MM_ICM_LCDIF … #define IMX8MM_ICN_MIPI … #define IMX8MM_ICM_USB1 … #define IMX8MM_ICM_USB2 … #define IMX8MM_ICM_PCIE … #define IMX8MM_ICN_HSIO … #define IMX8MM_ICM_SDMA2 … #define IMX8MM_ICM_SDMA3 … #define IMX8MM_ICN_AUDIO … #define IMX8MM_ICN_ENET … #define IMX8MM_ICM_ENET … #define IMX8MM_ICN_MAIN … #define IMX8MM_ICM_NAND … #define IMX8MM_ICM_SDMA1 … #define IMX8MM_ICM_USDHC1 … #define IMX8MM_ICM_USDHC2 … #define IMX8MM_ICM_USDHC3 … #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */
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