// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/G2L MTU3a Counter driver * * Copyright (C) 2022 Renesas Electronics Corporation */ #include <linux/clk.h> #include <linux/counter.h> #include <linux/mfd/rz-mtu3.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/types.h> /* * Register descriptions * TSR: Timer Status Register * TMDR1: Timer Mode Register 1 * TMDR3: Timer Mode Register 3 * TIOR: Timer I/O Control Register * TCR: Timer Control Register * TCNT: Timer Counter * TGRA: Timer general register A * TCNTLW: Timer Longword Counter * TGRALW: Timer longword general register A */ #define RZ_MTU3_TSR_TCFD … #define RZ_MTU3_TMDR1_PH_CNT_MODE_1 … #define RZ_MTU3_TMDR1_PH_CNT_MODE_2 … #define RZ_MTU3_TMDR1_PH_CNT_MODE_3 … #define RZ_MTU3_TMDR1_PH_CNT_MODE_4 … #define RZ_MTU3_TMDR1_PH_CNT_MODE_5 … #define RZ_MTU3_TMDR1_PH_CNT_MODE_MASK … /* * LWA: MTU1/MTU2 Combination Longword Access Control * 0: 16-bit, 1: 32-bit */ #define RZ_MTU3_TMDR3_LWA … /* * PHCKSEL: External Input Phase Clock Select * 0: MTCLKA and MTCLKB, 1: MTCLKC and MTCLKD */ #define RZ_MTU3_TMDR3_PHCKSEL … #define RZ_MTU3_16_BIT_MTU1_CH … #define RZ_MTU3_16_BIT_MTU2_CH … #define RZ_MTU3_32_BIT_CH … #define RZ_MTU3_TIOR_NO_OUTPUT … #define RZ_MTU3_TIOR_IC_BOTH … #define SIGNAL_A_ID … #define SIGNAL_B_ID … #define SIGNAL_C_ID … #define SIGNAL_D_ID … #define RZ_MTU3_MAX_HW_CNTR_CHANNELS … #define RZ_MTU3_MAX_LOGICAL_CNTR_CHANNELS … /** * struct rz_mtu3_cnt - MTU3 counter private data * * @clk: MTU3 module clock * @lock: Lock to prevent concurrent access for ceiling and count * @ch: HW channels for the counters * @count_is_enabled: Enabled state of Counter value channel * @mtu_16bit_max: Cache for 16-bit counters * @mtu_32bit_max: Cache for 32-bit counters */ struct rz_mtu3_cnt { … }; static const enum counter_function rz_mtu3_count_functions[] = …; static inline size_t rz_mtu3_get_hw_ch(const size_t id) { … } static inline struct rz_mtu3_channel *rz_mtu3_get_ch(struct counter_device *counter, int id) { … } static bool rz_mtu3_is_counter_invalid(struct counter_device *counter, int id) { … } static int rz_mtu3_lock_if_counter_is_valid(struct counter_device *counter, struct rz_mtu3_channel *const ch, struct rz_mtu3_cnt *const priv, int id) { … } static int rz_mtu3_lock_if_count_is_enabled(struct rz_mtu3_channel *const ch, struct rz_mtu3_cnt *const priv, int id) { … } static int rz_mtu3_count_read(struct counter_device *counter, struct counter_count *count, u64 *val) { … } static int rz_mtu3_count_write(struct counter_device *counter, struct counter_count *count, const u64 val) { … } static int rz_mtu3_count_function_read_helper(struct rz_mtu3_channel *const ch, struct rz_mtu3_cnt *const priv, enum counter_function *function) { … } static int rz_mtu3_count_function_read(struct counter_device *counter, struct counter_count *count, enum counter_function *function) { … } static int rz_mtu3_count_function_write(struct counter_device *counter, struct counter_count *count, enum counter_function function) { … } static int rz_mtu3_count_direction_read(struct counter_device *counter, struct counter_count *count, enum counter_count_direction *direction) { … } static int rz_mtu3_count_ceiling_read(struct counter_device *counter, struct counter_count *count, u64 *ceiling) { … } static int rz_mtu3_count_ceiling_write(struct counter_device *counter, struct counter_count *count, u64 ceiling) { … } static void rz_mtu3_32bit_cnt_setting(struct counter_device *counter) { … } static void rz_mtu3_16bit_cnt_setting(struct counter_device *counter, int id) { … } static int rz_mtu3_initialize_counter(struct counter_device *counter, int id) { … } static void rz_mtu3_terminate_counter(struct counter_device *counter, int id) { … } static int rz_mtu3_count_enable_read(struct counter_device *counter, struct counter_count *count, u8 *enable) { … } static int rz_mtu3_count_enable_write(struct counter_device *counter, struct counter_count *count, u8 enable) { … } static int rz_mtu3_lock_if_ch0_is_enabled(struct rz_mtu3_cnt *const priv) { … } static int rz_mtu3_cascade_counts_enable_get(struct counter_device *counter, u8 *cascade_enable) { … } static int rz_mtu3_cascade_counts_enable_set(struct counter_device *counter, u8 cascade_enable) { … } static int rz_mtu3_ext_input_phase_clock_select_get(struct counter_device *counter, u32 *ext_input_phase_clock_select) { … } static int rz_mtu3_ext_input_phase_clock_select_set(struct counter_device *counter, u32 ext_input_phase_clock_select) { … } static struct counter_comp rz_mtu3_count_ext[] = …; static const enum counter_synapse_action rz_mtu3_synapse_actions[] = …; static int rz_mtu3_action_read(struct counter_device *counter, struct counter_count *count, struct counter_synapse *synapse, enum counter_synapse_action *action) { … } static const struct counter_ops rz_mtu3_cnt_ops = …; #define RZ_MTU3_PHASE_SIGNAL(_id, _name) … static struct counter_signal rz_mtu3_signals[] = …; static struct counter_synapse rz_mtu3_mtu1_count_synapses[] = …; static struct counter_synapse rz_mtu3_mtu2_count_synapses[] = …; static struct counter_count rz_mtu3_counts[] = …; static const char *const rz_mtu3_ext_input_phase_clock_select[] = …; static DEFINE_COUNTER_ENUM(rz_mtu3_ext_input_phase_clock_select_enum, rz_mtu3_ext_input_phase_clock_select); static struct counter_comp rz_mtu3_device_ext[] = …; static int rz_mtu3_cnt_pm_runtime_suspend(struct device *dev) { … } static int rz_mtu3_cnt_pm_runtime_resume(struct device *dev) { … } static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_cnt_pm_ops, rz_mtu3_cnt_pm_runtime_suspend, rz_mtu3_cnt_pm_runtime_resume, NULL); static void rz_mtu3_cnt_pm_disable(void *data) { … } static int rz_mtu3_cnt_probe(struct platform_device *pdev) { … } static struct platform_driver rz_mtu3_cnt_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_ALIAS(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_IMPORT_NS(…);
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